Capacitance Transient Spectroscopy Research Articles

Admittance Spectroscopy Study of Defects in β-Ga2O3

We present a comprehensive investigation of electrically active defects and transport properties in commercial (2¯01) edge-defined film-fed growth β-Ga2O3 using admittance spectroscopy measurements from 14 K up to 450 K. Isothermal capacitance-frequency measurements were conducted from 410 to 450 K to resolve a defect ∼0.8 eV below the conduction band edge and compared with deep-level transient spectroscopy and isothermal capacitance transient spectroscopy measurements. We report significant non-Arrhenius behavior of a defect ∼100 meV below the conduction band and apply the Arrhenius transformation matching method to extract its temperature-dependent activation energy and capture cross-section in the temperature range of 75 to 195 K. At low temperatures (<50 K), we use bias-dependent admittance spectroscopy to extract the electron mobility in β-Ga2O3 from the modified dielectric relaxation frequency. Finally, we discuss the potential of admittance spectroscopy for defect characterization in wide bandgap semiconductors in terms of the defect detection range, instrument requirements, and the frequency-temperature experiment space.

Auxiliary Diagnostic Signal for Deep-Level Detection.

We propose and demonstrate that temperature-dependent curve-fitting error values of the Schottky diode I-V curve in the forward regime can be an auxiliary diagnostic signal as the temperature-scan Capacitance DLTS (CDLTS) signals and helps to work time-efficiently with high accuracy when using the Laplace Transform (LT)-DLTS or Isothermal Capacitance transient spectroscopy (ICTS) method. Using Be-doped GaAs showing overlapping DLTS signals, we verify that the LT-DLTS or ICTS analysis within a specific temperature range around the characteristic temperature Tpeak coincides well with the results of the CDLTS and Fourier Transform DLTS performed within the whole temperature range. In particular, we found that the LT-DLTS signals appeared intensively around Tpeak, and we confirmed it with the ICTS result. The occurrence of the curve fitting error signal is attributed to the relatively increased misfit error by the increased thermal emission from the deep-level trap in the case near the Tpeak, because the applied transport model excludes defect characteristics.

Insight into the suppression mechanism of bulk traps in Al2O3 gate dielectric and its effect on threshold voltage instability in Al2O3/AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors

Bulk trapping and its effects on threshold voltage hysteresis (ΔVTH) in Al2O3/AlGaN/GaN metal–oxide-semiconductor high electron mobility transistors (MOS-HEMTs) have been identified by a combination of isothermal capacitance transient spectroscopy (ITS) and X-ray photoelectron spectroscopy (XPS). A post deposition annealing (PDA) at 500 °C in O2 ambient is confirmed to be an effective way to reduce the bulk traps in an atomic layer deposited (ALD)-Al2O3 film as it contributes to the suppressed ΔVTH in Al2O3/AlGaN/GaN MOS-HEMTs. The interface and bulk trapping behavior that account for ΔVTH, have been distinguished by ITS. It is revealed that continual charging of bulk traps in the Al2O3 gate dielectric occurred once the gate bias of the MOS-HEMTs is applied exceeding +3 V, which leads to the degraded ΔVTH as well as subthreshold slopes in transfer characterization. Such bulk traps probably stem from the Al-O-H component in the as-deposited Al2O3 layers, as detected by XPS. Energy band simulation further illustrates the capture process of the bulk traps, verifying the physical relationship between bulk-trapping and ΔVTH in GaN-based MOS-HEMTs.

Characterization of deep-level defects in highly-doped silicon with asymmetric structure by transient capacitance spectroscopy

Characterization of deep-level defects in highly-doped silicon with asymmetric structure by transient capacitance spectroscopy

Charge Trap States of SiC Power TrenchMOS Transistor under Repetitive Unclamped Inductive Switching Stress.

Silicon carbide (SiC) has been envisioned as an almost ideal material for power electronic devices; however, device reliability is still a great challenge. Here we investigate the reliability of commercial 1.2-kV 4H-SiC MOSFETs under repetitive unclamped inductive switching (UIS). The stress invoked degradation of the device characteristics, including the output and transfer characteristics, drain leakage current, and capacitance characteristics. Besides the shift of steady-state electrical characteristics, a significant change in switching times points out the charge trapping phenomenon. Transient capacitance spectroscopy was applied to investigate charge traps in the virgin device as well as after UIS stress. The intrinsic traps due to metal impurities or Z1,2 transitions were recognized in the virgin device. The UIS stress caused suppression of the second stage of the Z1,2&amp;nbsp; transition, and only the first stage, Z10, was observed. Hence, the UIS stress is causing the reduction of multiple charging of carbon vacancies in SiC-based devices.

Current Transient Spectroscopic Study of Vacancy Complexes in Diamond Schottky p-i-n Diode

The present state-of-the-art of junction-based diamond electronic devices is limited by the challenges inherent to the synthesis of n-type layers, where the dopant itself forms defect complexes that are donor compensating centers. Recently, the fabrication of diamond Schottky p-i-n diodes (SPINDs) by chemical vapor deposition (CVD) of intrinsic diamond films followed by an n-type layer on p-type diamond substrates has been reported to demonstrate excellent diode-like behavior with high rectification factors and surface barrier height at elevated temperatures. However, due to the ultrawide bandgap of diamond and small contact area of the devices, it is challenging to characterize the defect centers that limit the performance of the SPINDs using conventional capacitance transient spectroscopy. In this article, we report the characterization of defect centers in the diamond SPINDs with a contact area of 280 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}\,\,\times \,\,280\,\,\mu \text{m}$ </tex-math></inline-formula> using current transient spectroscopy (CTS), which measures thermally induced emission rates from trap centers through change in device current instead of junction capacitance. The CTS scans in the temperature range 80–800 K revealed the presence of five trap-related peaks. Results from density functional theory (DFT) calculations were used to identify the nature of the traps. While most of the detected traps were identified to be vacancy complexes coupled to phosphorus and hydrogen impurities, one trap has been identified as single carbon vacancy. Most of the phosphorus-related defect complexes were observed to be in neutral and/or negative charge states and were identified as acceptor-like states.

Depth profiles of electron traps generated during reactive ion etching in n-type 4H-SiC characterized by using isothermal capacitance transient spectroscopy

Electron traps generated during the reactive ion etching (RIE) process in n-type 4H-SiC are investigated using the deep-level transient spectroscopy technique and isothermal capacitance transient spectroscopy (ICTS) technique. Two electron traps of the Z1/2 center (EC−0.64eV) and the EH3 center (EC−0.74eV) are detected in the RIE-etched sample by ICTS measurement at 300 K. A method is proposed to determine the depth profiles of the electron traps that are localized near the etched surface, whereby a depth profile is extracted from the dependence of averaged trap density on the depletion layer width. An exponential distribution is assumed as the depth profile of the electron traps generated during the RIE process. The extracted depth profile was confirmed to be consistent with that determined by the double-correlation method. An appropriate function for the depth profile of carrier traps is assumed and the dependence of the averaged trap density on the depletion layer width is analyzed, which enables the extraction of a depth profile that has both higher depth resolution and higher resolution in the carrier trap density with the proposed method than that with the double-correlation method.

Photoionization cross section ratio of nitrogen-site carbon in GaN under sub-bandgap-light irradiation determined by isothermal capacitance transient spectroscopy

The ratio of the photoionization cross sections () of carbon substituting at the nitrogen site [CN (0/−)] in n-type GaN, which is detected as a hole trap H1 ( + 0.85 eV) under sub-bandgap-light irradiation (390 nm), is determined with isothermal capacitance transient spectroscopy (ICTS). The current-injection ICTS and the sub-bandgap-light-excited ICTS were compared for the same p+-n junction diode, whereby the hole occupancy ratio () was obtained. Analysis of the dependence of on the temperature gave of 3.0 was then used to estimate the charge state of CN (0/−) under sub-bandgap-light irradiation.

Capacitance and Current Deep-Level Transient Fourier Spectroscopy (DLTFS) for the Characterization of Defect States in Mg-Doped GaN-on-Si p+n Diodes

GaN is a promising semiconductor for high power and high frequency devices such as pn diodes [1] and high electron mobility transistors (HEMTs). Moreover, GaN grown on silicon substrates allow the study of new technologies [2]. However, many defects can degrade the performance of the GaN based devices and occur in the form of native point defects, impurities and extended defects. Few defect states were found, such as nitrogen vacancies, Mg dopants or C impurities but they are not well explained. Therefore, in this work we investigated the defect characteristics of Mg-doped GaN-on-Si p+n diodes using the Deep-Level Transient Fourier Spectroscopy (DLTFS). This technique is based on the measurement of capacitance (C-DLTFS) or current (I-DLTFS) transients during charge release from filled traps. It is an electrical characterization technique used to determine and calculate the density N T, the energy position and the capture cross-section σ T of defect states.The p+n diodes were grown by MOCVD on Si substrates. The p+n structure was composed of a 400 nm thick Mg-doped p +-GaN layer at 6x1019 cm-3 and of a 750 nm thick Si-doped n-GaN layer at 3x1016 cm-3. The DLTFS measurements have been performed between 100 K and 425 K with a dynamic signal of frequency of 1 MHz for various reverse voltages U R and pulse voltages U P = -0.5 V for C-DLTFS and U P = 3 V for I-DLTFS. Capacitance-voltage measurements (not shown) evidenced a graded and non-linear p + n junction.The C-DLTFS spectrum (fig 1.a) shows two positive peaks (T1 and T2) respectively at 130 K and at 330 K and the I-DLTFS spectrum (fig 1.b) shows a positive peak at 390 K. For the peaks at high temperature on C-DLTFS and I-DLTFS spectra, average E A values of about 0.83 eV and 0.81 eV were extracted for both spectra respectively (fig 1.c). So, these two peaks are related to the same defect state. Besides, shifts to high temperature values (opposite as for the Poole-Frenkel effect) were observed on both spectra and this could indicate interface traps. Also, when increasing U P to positive values (not shown), the T1 amplitude increases while the T2 amplitude decreases [3]. This defect state might be associated with hole traps at the interface of the p+n junction on the p+ -side of the junction and are tentatively assigned to CN states [4]. For the peak at low temperature (T1), no temperature shift with U R was observed indicating bulk traps in the n-region and an activation energy (E A) of about 0.23 eV was extracted (fig 1.c). This defect is commonly assigned to dislocations related to VN defects or to VN-VG complexes. Moreover, Mg dopants (p-type) for this doping level have an E A value of about 0.25 eV very close to the T1 E A value. So, the graded and non-linear p + n junction could be explained by the Mg dopants diffusion into the n-type region along dislocations, as previously observed [5].[1] Y. Zhang et al., “High-Performance 500 V Quasi- and Fully-Vertical GaN-on-Si pn Diodes,” IEEE Electron Device Lett., vol. 38, no. 2, pp. 248–251, Feb. 2017.[2] M. Ishida et al., “GaN on Si Technologies for Power Switching Devices,” IEEE Trans. Electron Devices, vol. 60, no. 10, pp. 3053–3059, Oct. 2013.[3] Y. Lechaux et al., “Characterization of defect states in Mg-doped GaN-on-Si pn diodes using deep-level transient Fourier spectroscopy,” Semicond. Sci. Technol., vol. 36, no. 2, p. 024002, Dec. 2020.[4] T. Narita et al., “The origin of carbon-related carrier compensation in p-type GaN layers grown by MOVPE,” J. Appl. Phys., vol. 124, no. 21, p. 215701, Dec. 2018.[5] S. Usami et al., “Direct evidence of Mg diffusion through threading mixed dislocations in GaN p–n diodes and its effect on reverse leakage current,” Appl. Phys. Lett., vol. 114, no. 23, p. 232105, Jun. 2019. Figure 1

Origin of the retention loss in ferroelectric Hf0.5Zr0.5O2-based memory devices

For the decade, ferroelectric hafnium oxide films are attracting the interest as a promising functional material for nonvolatile ferroelectric random access memory due to full scalability and complementary metal-oxide-semiconductor integratability. Despite the significant progress in key performance parameters, particularly, the readout charge and voltage as well as the endurance, the developed devices can only be implemented by the electronics industry if they exhibit a standard retention time of 10 years. Material engineering modifies not only target ferroelectric properties, but also the retention time. To understand how to maintain the sufficient retention, the physical mechanism behind it should be clarified. For this purpose, we have fabricated the capacitor memory cell with a high rate of retention loss. Comparing the device performance with the results of capacitance transient spectroscopy, operando hard X-ray photoelectron spectroscopy and in situ piezoresponse force microscopy, we have concluded that the retention loss is caused by the accumulation of the positively charged oxygen vacancies at the interfaces with capacitor electrodes. The redistribution of charges during long-term storage of information is fully defined by the domain structure in memory cell.

Evolution of the electrical characteristics of Cu(In,Ga)Se2 devices with sodium content

The impact of sodium on the electrical properties of Cu(In,Ga)Se2 (CIGS) thin films and corresponding solar cells was investigated by preparing nearly alkali-free CIGS layers and doping them with different Na amounts via NaF post-deposition treatment (PDT) at temperatures between 110 and 400 °C. The mean Na concentrations in the CIGS layers ranged from 0.1 to 400 ppm. Sodium was found also in the grain interior even for the lowest PDT temperature. All samples were subjected to extensive electrical characterization: current–voltage, capacitance profiling, conductivity, steady-state, and transient capacitance spectroscopy. A continuous increase in open-circuit voltage VOC and fill factor FF, an accompanying increase in hole density and mobility, and a decrease in secondary barriers responsible for the distortion of current–voltage characteristics were observed with increasing sodium content. An abrupt change in defect spectra and a dominant transport mechanism was found for PDT temperatures T(PDT) of ≥150 °C. We attribute a further improvement in VOC observed above 150 °C PDT temperature to the reduced concentration of recombination centers with increased sodium content. An explanation of both gradual evolution and the abrupt change is proposed based on passivation of grain boundaries and interfaces by sodium.

Deep levels model identification in semiconductor barrier structures

Semiconductor barrier structures are essential elements of modern integrated electronics. The band theory explains properties of barrier structures using deep levels in the semiconductor band gap. The relentless interest in studying the characteristics of deep levels is due to practical needs, ambiguous interpretations and scatters of experimental results obtained by different researchers. In order to increase the accuracy of the measurements, a modified capacitive deep-level transient spectroscopy technic of has been developed. A mathematical model of the hardware transformations of the barrier structure capacitance transient signal is developed and provided in this article. The model considers the nonexponentiality of the capacitance transient and the spectrometer hardware transformations nonlinearity. There are the results of the deep levels experimental studies in silicon diodes and the model parametric identification. The technic makes it possible to reduce by five or more times the six-sigma confidence interval for the discrete deep level activation energy determining in comparison with the round robin test results of ASTM F978-02.

Electron traps formed by gamma-ray irradiation in homoepitaxial n-type GaN and their annealing behavior

Gamma-ray irradiations of up to 500 kGy on homoepitaxial n-type GaN layers were carried out, and the formation of electron traps was investigated by deep-level transient spectroscopy (DLTS) using Ni Schottky barrier diodes (SBDs). Before performing DLTS, current–voltage (I–V) and capacitance–voltage (C–V) measurements of the SBDs were performed and it was found that there was no change in the net donor concentration, ideality factor, and Schottky barrier height after irradiation. In the DLTS measurements, two new peaks, labeled G1 and G2, were observed after irradiation. The filling pulse width dependence of G1 revealed that the peak consists of two electron trap levels, labeled G1a (EC − 0.13 eV) and G1b (EC − 0.14 eV). Isothermal capacitance transient spectroscopy measurements of samples with different Schottky barrier heights showed that the G2 peak is a complex peak consisting of at least three electron traps, labeled G2a (EC − 0.80 eV), G2b (EC − 0.98 eV), and G2c (EC − 1.08 eV). The production rates (formation rates of traps by gamma-ray irradiation) for each trap were obtained. Finally, we investigated the annealing behavior of each trap and found that G1b and G2b decreased by the same amount with increasing annealing temperature, suggesting that the behavior originates from a recombination of vacancy–interstitial (Frenkel) pairs.

Peculiarities of electron emission from high-density deep levels of nanodefects in oxygen-implanted silicon

The peculiarities of electron emission from electronic states of nanodefects formed at the early stages of oxygen precipitation in oxygen-implanted silicon annealed at 700°C were investigated with a combination of capacitance and current transient spectroscopy of the space charge region (SCR) in semiconductors. It was established that the particular properties of acceptor-like states are due to their high density and their localization at the back side of the implanted region. A model is suggested that explains an apparent emission rate slowdown and the appearance of an unexpected sign of capacitance relaxation signal as a result of the non-monotonic shape of the potential of the Schottky-diode.

Dual-color-sub-bandgap-light-excited isothermal capacitance transient spectroscopy for quick measurement of carbon-related hole trap density in n-type GaN

A quick method is proposed for measurement of the carbon-related hole trap (H1: +0.87 eV) density in an n-type GaN homoepitaxial layer using dual-color-sub-bandgap-light-excited isothermal capacitance transient spectroscopy. Shorter wavelength (390 nm) light irradiation is employed to cause the hole traps to be in the hole-occupied state. Longer wavelength (660 nm) light irradiation is then used to emit the hole from the trap to the valence band. The photoemission of holes is much quicker than the thermal emission, which reduces the measurement time. The trap density can be calculated from the capacitance transient.

Editors’ Choice—Electrical Properties and Deep Traps in α-Ga2O3:Sn Films Grown on Sapphire by Halide Vapor Phase Epitaxy

Films of α-Ga2O3 doped with Sn were grown by halide vapor phase epitaxy (HVPE) on planar and patterned sapphire substrates. For planar substrates, with the same high Sn flow, the total concentration of donors was varying from 1017 cm−3 to high 1018 cm−3. The donor centers were shallow states with activation energies 35–60 meV, centers with levels near Ec–(0.1–0.14) eV (E1), and centers with levels near Ec–(0.35–0.4) eV (E2). Deeper electron traps with levels near Ec−0.6 eV (A), near Ec−0.8 eV (B), Ec−1 eV (C) were detected in capacitance or current transient spectroscopy measurements. Annealing of heavily compensated films in molecular hydrogen flow at 500 °C for 0.5 h strongly increased the concentration of the E1 states and increased the density of the E2 and A traps. For films grown on patterned substrates the growth started by the formation of the orthorhombic α-phase in the valleys of the sapphire pattern that was overgrown by the regions of laterally propagating α-phase. No improvement of the crystalline quality of the layers when using patterned substrates was detected. The electric properties, the deep traps spectra, and the effects of hydrogen treatment were similar to the case of planar samples.

Study of defects in β-Ga2O3 by isothermal capacitance transient spectroscopy

The authors use isothermal capacitance transient spectroscopy to detect three deep defects located at approximately 0.6, 0.8, and 1.0 eV below the conduction band of β-Ga2O3 materials. The electrical properties of these defects such as their capture cross sections and concentrations are characterized, and their potentially adverse effects on power electronic devices are discussed. Because the isothermal capacitance transient spectroscopy method is implementable by instruments intended for steady-state capacitance-voltage measurement, it is promising for use as an effective characterization and monitoring tool for deep defects in β-Ga2O3 and other wide bandgap semiconductors.

High-temperature deep-level transient spectroscopy system for defect studies in wide-bandgap semiconductors.

Full investigation of deep defect states and impurities in wide-bandgap materials by employing commercial transient capacitance spectroscopy is a challenge, demanding very high temperatures. Therefore, a high-temperature deep-level transient spectroscopy (HT-DLTS) system was developed for measurements up to 1100 K. The upper limit of the temperature range allows for the study of deep defects and trap centers in the bandgap, deeper than previously reported by DLTS characterization in any material. Performance of the system was tested by carrying out measurements on the well-known intrinsic defects in n-type 4H-SiC in the temperature range 300-950 K. Experimental observations performed on 4H-SiC Schottky diodes were in good agreement with the literature. However, the DLTS measurements were restricted by the operation and quality of the electrodes.

Deep traps localization in AlGaN/GaN MIS-HEMTs by a comparative study using capacitance and current deep level transient spectroscopies

In this study, deep traps in multiple-finger normally-off AlGaN/GaN metal-insulator-semiconductor high-electron mobility transistors (MIS-HEMTs) were identified. The localization of these traps has been established by a comparative study using capacitance and current deep level transient spectroscopies (DLTS). The Cgd-DLTS measurements cover the GaN buffer region between the gate and drain contacts. On the other hand, the IDS-DLTS measurements cover the channel region in GaN including the zone under the gate. Two electron traps, E2 (0.31eV) and E4 (0.5eV) have been detected. They are respectively attributed to reactive ion etching (RIE) induced surface damage. These two traps are more likely located in the GaN channel close to the gate. Two other deep electron traps E5 (0.64eV) and E6 (0.79eV) have also been detected and are localized in the GaN buffer layer.

Study of deep traps in AlGaN/GaN high-electron mobility transistors by electrical characterization and simulation

The localization of deep traps in normally-off AlGaN/GaN metal-oxide-semiconductor channel high-electron mobility transistors has been established by means of capacitance and current deep level transient spectroscopies (DLTS). Electrical simulations of the total current density between the drain and source contacts, the electron density, and the equipotential line distribution helped to understand the transport mechanisms into the device and to determine the zone probed by DLTS measurements. By changing the drain-source voltage in current DLTS or the reverse bias in capacitance DLTS, we demonstrated that we can choose to probe either the region below the gate or the region between the gate and drain electrodes. We could then see that defects related to reactive ion etching induced surface damage, expected to be formed during the gate recess process, were located only under the gate contact whereas native defects were found everywhere in the GaN layer. Thanks to this method of localization, we assigned a trap with an EC – 0.5 eV to ion etching induced damage.