Capacitance-to-voltage Converter Research Articles

High-Power-Efficiency Readout Circuit Employing Average Capacitance-to-Voltage Converter for Micro-Electro-Mechanical System Capacitive Accelerometers.

A capacitance-to-voltage converter (CVC) is proposed in this paper and applied to a readout circuit for a micro-electro-mechanical system (MEMS) accelerometer to improve the power efficiency. In a traditional readout circuit, the front-end CVC has to operate at a high sampling frequency to resist thermal noise deterioration due to the large parasitic capacitance introduced by the mechanical sensing element. Thus, the back-end analog-to-digital converter (ADC) also has to operate at a high sampling frequency to avoid noise aliasing when sampling the output signal of the CVC, which leads to high power consumption. The average CVC technique is proposed in this paper to reduce the sampling frequency requirement of the back-end ADC and thus reduce the power consumption. Both the traditional readout circuit and the proposed readout circuit are simulated with a commercial 0.18 μm BCD process. The simulation results show that noise aliasing occurs, and the noise power spectral density (PSD) of the traditional readout circuit increases by 12 dB when the sampling frequency of back-end ADC is reduced by 24 dB. However, in the proposed readout circuit, a noise aliasing effect does not occur. Moreover, the proposed readout circuit reduces the power consumption by 53% without thermal noise deterioration. In addition, the proposed CVC circuits are fabricated in an 0.18 μm BCD process, and the test results show that the presented readout circuit based on the average CVC technique can obtain better performance than the traditional CVC-based readout circuit.

An accurate Verilog-A based model for MEMS capacitive accelerometer

This paper presents an accurate macro model for a capacitive micro accelerometer using Verilog-A tool. For this purpose, first the accelerometer is simulated in COMSOL software. Then, considering the simplified physics of the accelerometer, a preliminary Verilog-A model is derived, which is not accurate enough. This initial model has been modified by using mathematical tools and adapting to the results of COMSOL. Furthermore, a switched-capacitor based capacitance to voltage converter (CVC) is used as a readout circuit to validate the proposed model. The CVC is designed, simulated and optimized in the Cadence software by using a 65 nm CMOS technology. In order to reduce low-frequency non-idealities such as flicker noise and DC offsets, a chopper-stabilization technique is used. The power consumption for a 1.2 V supply is 140 μW. Simulation results show a good agreement between COMSOL results and simulation of the proposed model in the Cadence.

Capacitance-to-voltage converter employing parallel-series passive charge integrator for low noise power efficient MEMS capacitive sensor

Parallel-series passive charge integrator (PSPI) based capacitance-to-voltage converter (CVC) is proposed in this paper to reduce the noise floor of readout circuit for MEMS capacitive sensor with high power efficiency in terms of the figure of merit (FoM). For MEMS capacitive accelerometer, open-loop structure is preferred for its low power consumption. However, in the open-loop structure, the capacitance variation of sensing element is limited to femto-farad level in order to overcome nonlinearity. As a result, the thermal noise from parasitic capacitance becomes significant, which leads to low SNR. Traditional oversampling method can reduce the parasitic-induced noise, but leads to low power efficiency. In this work, the PSPI-CVC is proposed to reduce the parasitic-induced noise with high power efficiency. The PSPI-CVC is designed by a commercial 0.18 μm CMOS process. The transistor-level simulation results show that, compared to the traditional CVC, the PSPI-CVC can improve the SNR by 24 dB without increase of the power consumption. Compared with the other similar works, the proposed readout circuit achieves competitive FoM1 (FoM1 =20.2pJ)and the best FoM2 (FoM2).

Monitoring System With Cross-Type Capacitive Plantar Pressure Sensor

This study presents a monitoring system with a $4\times4$ handmade cross-type capacitive plantar pressure (CCPP) sensor. This system includes a prototype detection module and a display interface, and it is implemented as a wearable device. The prototype detection module consists of a low dropout regulator (commercial IC) utilized to regulate a stable DC voltage with 3.7 V Li-ion battery for a whole wearable device and a customized capacitance-to-digital converter (CDC) chip is employed to convert capacitances into the digital data. The CDC includes a capacitance-to-voltage converter (CVC) and 10-bit successive approximation register analog-to-digital converter are fabricated via the TSMC $0.18~\mu \text{m}$ 1P6M 3.3 V process. CVC is characterized by its selectability of detection points from 1 to 64 ( $8\times8$ cross-type capacitive array). This type of converter is controlled by digital codes of a field-programmable gate array (FPGA) and has embedded functions of a self-separated input signal, which is applied to scan each detection point of the cross-type capacitive sensors, and a crosstalk attenuation (CA) is used to reduce parasitic capacitances and the effects of relative humidity and temperature of the environment for cross-type capacitive sensors. To demonstrate improvements of the CA, a multi-physics simulation software, COMSOL Multiphysics, was utilized to verify the performance of the CA. The handmade $4\times4$ CCPP sensor is modeled in COMSOL Multiphysics and simulated with/without CA. Finally, the simulated results reveal that the function of CA can reduce parasitic capacitances and the effects of the relative humidity and temperature caused by the environment effectively at the femtofarad level. The cross-type structure of a capacitive array has an advantage due to an $M\times N$ array, which only requires $M + N$ tracks of input/output (I/O) ports to reduce the complexity of I/O connections. The measured results of the prototype detection module shown on the display interfaces reveal the positions and strengths of the corresponding capacitances of the CCPP sensor. The range of sensing capacitance is from 0 pF to 5.406 pF, the minimum sensing step is 15 fF, the accuracies of the handmade CCPP sensor and prototype detection module are −11.6/9.96 % and −8.65/5.54 %, respectively, and the sensitivity is 8 fF/N. The conversion time for one capacitance is 0.28 ms, and the maximum conversion time for 64 capacitances is 18.29 ms.

Detection System for Capacitive Plantar Pressure Monitoring

This study presents a detection system with a prototype acquisition module and display interface for capacitive plantar pressure monitoring. The detection system mainly focuses on a systemlevel design (not a system on chip). The prototype acquisition module consists of commercial ICs and self-designed chips: A capacitance-to-voltage converter (CVC) and a 10-bit fully differential successive approximation register analog-to-digital converter are fabricated by the TSMC 0.18 μm 1P6M 3.3 V process. The feature of the CVC is selectable for the detection points from 1 to 64, which is controlled by the digital codes of a field-programmable gate array (FPGA). It also has the embedded functions of crosstalk attenuation (CA) for cross-type capacitive sensors and a self-separated input signal for capacitive plantar pressure monitoring. The CA can effectively reduce parasitic capacitances and influences of the temperature and relative humidity of the environment: An M×N array only requires M + N tracks of I/O ports to reduce detected complexity. The measured results shown on the display interfaces reveal the positions and amplitudes (voltage swings) of the corresponding capacitances. The conversion time for one capacitance is 0.4 ms, and the maximum conversion time for 64 capacitances is 25.6 ms. A handmade cross-type capacitive array and a cross-type capacitive plantar pressure sensor are used to demonstrate the detection system.

A low noise capacitive MEMS accelerometer with anti-spring structure

This work reports a capacitive MEMS accelerometer designed for seismic applications. The asymmetrical anti-spring structure is used and the device is microfabricated using SOI technology. Two capacitive readout methods, namely, capacitance-to-voltage-converter (CVC) and a commercial sigma-delta modulator, are introduced for comparison in the device characterization. For both methods, the accelerometer has a frequency dynamic range of 0-158 Hz. The sensitivity and non-linearity of the sensor is 53 fF/g (21.3 mV/g), 0.03% by the sigma-delta modulator, while the CVC method is 3.78 mV/g with the non-linearity 0.04%. As for the resolution, both methods have detected the lab's background noise of 11.5 μg/Hz at 0.03 Hz and have exhibited the resolution of the sensor is better than 10 μg/Hz. Regardless of the difference in parameter selection for the circuits, the CVC method has a much lower noise floor (51.8 ng/Hz at 1 Hz) than sigma-delta readout configuration (10 μg/Hz at 1 Hz). The proposed MEMS accelerometer based on anti-spring structures shows its high sensitivity and low noise performance, demonstrating its potential in seismic applications.

An accurate and power‐efficient period‐modulator‐based interface for grounded capacitive sensors

SummaryA low‐power and high‐resolution capacitance‐to‐period converter (CPC) based on period modulation (PM) for subnanometer displacement measurement systems is proposed. The presented circuit employs the interface developed in a previous work, “a grounded capacitance‐to‐voltage converter (CVC) based on a zoom‐in structure,” further improving its performance through a symmetrical design of the applied autocalibration technique. The scheme is based on the use of a relaxation oscillator. To minimize the error contributed by the CPC circuitry, different precision techniques such as chopping, autocalibration, and active shielding are applied. The proposed CPC is realized in a 0.18‐μm complementary metal‐oxide‐semiconductor (CMOS) technology, occupies an area of 0.5 mm2, and consumes 135 μA from a 2‐V power supply. In order to achieve optimal performance and avoid overdesigning, a noise estimation of various parts of the CPC has been done. Accordingly, for a 10‐pF sensor capacitance, the overall CPC demonstrates a capacitance resolution of 0.5 fF for a latency of 128 microseconds, corresponding to an effective number of bits (ENOB) of 12.5 bits and an energy efficiency of 6 pJ/step. The nonlinearity error has been evaluated as well, resulting in a less than 0.03% full‐scale span (FSS).

Toward High Throughput Core-CBCM CMOS Capacitive Sensors for Life Science Applications: A Novel Current-Mode for High Dynamic Range Circuitry.

This paper proposes a novel charge-based Complementary Metal Oxide Semiconductor (CMOS) capacitive sensor for life science applications. Charge-based capacitance measurement (CBCM) has significantly attracted the attention of researchers for the design and implementation of high-precision CMOS capacitive biosensors. A conventional core-CBCM capacitive sensor consists of a capacitance-to-voltage converter (CVC), followed by a voltage-to-digital converter. In spite of their high accuracy and low complexity, their input dynamic range (IDR) limits the advantages of core-CBCM capacitive sensors for most biological applications, including cellular monitoring. In this paper, after a brief review of core-CBCM capacitive sensors, we address this challenge by proposing a new current-mode core-CBCM design. In this design, we combine CBCM and current-controlled oscillator (CCO) structures to improve the IDR of the capacitive readout circuit. Using a 0.18 μm CMOS process, we demonstrate and discuss the Cadence simulation results to demonstrate the high performance of the proposed circuitry. Based on these results, the proposed circuit offers an IDR ranging from 873 aF to 70 fF with a resolution of about 10 aF. This CMOS capacitive sensor with such a wide IDR can be employed for monitoring cellular and molecular activities that are suitable for biological research and clinical purposes.

Design trade‐offs of a capacitance‐to‐voltage converter with a zoom‐in technique for grounded capacitive sensors

SummaryThis paper presents a low‐power, high‐precision capacitance‐to‐voltage converter (CVC) for grounded capacitive sensors. To measure very small capacitance variations in the presence of a large offset capacitance, a new zoom‐in structure is proposed. The major non‐idealities of the CVC such as the settling error, charge injection, and parasitic capacitance of the switches are minimized through an optimized design. Accordingly, it is shown that the zoom‐in technique can significantly reduce many of these errors. The effect of the parasitic capacitances around the sensor capacitance is significantly reduced by using a switched‐capacitor‐based active‐shielding technique. The interface is designed as an integrated circuit using a standard 0.18‐μm CMOS technology. Simulation results show that for a sensor capacitor with a nominal value of 10 pF, variation of only 200 fF, and parasitic capacitance of up to 20 pF, a worst‐case capacitance error of 0.2 fF can be achieved by taking into account the layout mismatches and the interconnection effects. The achieved latency is 100 μs, and the CVC consumes only 80 μA from a 2‐V power supply. The simulated input capacitance resolution for this latency is 123 aF, which is quite close to our calculated resolution (126 aF). This resolution corresponds to an energy efficiency of 9.82 pJ/Step. A temperature sweep simulation has been performed over the temperature range from −45°C to 125°C to demonstrate the small thermal drift of the designed circuit.

An Energy-Efficient Miniaturized Intracranial Pressure Monitoring System

A miniaturized pressure-sensing microsystem targeting intracranial pressure monitoring is presented. The system takes full advantage of Invensense MEMS-CMOS process to heterogeneously integrate the sensor and interface. This integration type requires no fabrication postprocessing and results in sub-pF sensor-interface parasitic interconnection capacitance C, which is an order of magnitude smaller than previously reported C,s. Since energy efficiency is of main concern, the minimum energy consumption for maintaining a certain signal-to-noise ratio (SNR) is analytically calculated and compared for two energy-efficient sensor front ends, namely, the switched-capacitor (SC) capacitance-to-voltage converter (CVC) and the successive approximation register (SAR) capacitance-to-digital converter (CDC). The comparison reveals for small values of C, and for low-to-moderate SNR, the SAR CDC outperforms the SC CVC in terms of power consumption. Heterogeneous integration of sensor and CMOS electronics results in only 720 fF of C, which enables direct SAR capacitance-to-digital conversion. Correlated double sampling is also integrated into the proposed SAR switching scheme to combat 1/f noise and the input-referred offset voltage of the comparator. The entire pressure-sensing system measures 2.2 × 2.6 × 0.4 mm 3 in size, consumes 130 nW at 60-Hz sampling rate, and obtains 57-dB SNR with 0.2% sensor-electronics combined linearity over 520-mmHg pressure range.

Programmable Low-Power Low-Noise Capacitance to Voltage Converter for MEMS Accelerometers.

In this work, we present a capacitance-to-voltage converter (CVC) for capacitive accelerometers based on microelectromechanical systems (MEMS). Based on a fully-differential transimpedance amplifier (TIA), it features a 34-dB transimpedance gain control and over one decade programmable bandwidth, from 75 kHz to 1.2 MHz. The TIA is aimed for low-cost low-power capacitive sensor applications. It has been designed in a standard 0.18-μm CMOS technology and its power consumption is only 54 μW. At the maximum transimpedance configuration, the TIA shows an equivalent input noise of 42 fA/ at 50 kHz, which corresponds to 100 μg/.

EFFICIENT CAPACITANCE SENSING FOR WIRELESS HEALTH MONITORING SYSTEM

This paper presents a low power capacitance to voltage converter (CVC) circuit using two differential amplifier circuits, two Schottky rectifier diodes constructed in symmetrical manner and combined with instrumentation amplifier circuits. The differential capacitance to voltage simulation work has been realized with cheap discrete components. Combination energy from solar, vibration and heat is expected to be used to source the capacitance circuit. Constant dc voltage of 3 V has been used to source the CVC circuit in this work. It is found by the simulation, the converter circuit consumes 3.9 mW of total power, operates at 40 kHz using 400 mV excitation signal. The circuit is able to detect changes of capacitance from 4 – 12.5 pF using reference capacitance of 5 pF. Sensitivity of 0.132 mV for 1 fF capacitance change has been observed in the circuit. This circuit is suitable for wireless health monitoring system.

A Highly Linear, Small-Area Analog Front End With Gain and Offset Compensation for Automotive Capacitive Pressure Sensors in 0.35-<inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>m CMOS

This paper presents a highly linear, small-area analog front end with gain and offset compensation for automotive capacitive pressure sensor. We propose a capacitance-tovoltage converter circuit that measures the capacitance value of the capacitive sensor with the high accuracy and linearity. In this paper, the linearity of the analog front end is guaranteed using full-analog gain and an offset calibration circuit. The proposed design is implemented using CMOS 0.35 μm technology with an active area of 1.94 mm x 1.94 mm. The full output range is from 0.5 to 4.5 V. The ratiometricity is within ±0.7% when the supply voltage is changed by ±10%. The power consumption is 25 mW from a 5 V supply. The output accuracy is within ±1% with respect to Process, Voltage, Temperature variations.

MEMS 가속도센서를 위한 CMOS Readout 회로

본 논문에서는 MEMS(Micro Electro Mechanical System) 가속도센서를 위한 CMOS readout 회로를 설계하였다. 설계된 CMOS readout 회로는 MEMS 가속도 센서, 커패시턴스-전압 변환기(CVC), 그리고 2차 스위치드 커패시터 <TEX>${\Sigma}{\Delta}$</TEX> 변조기로 구성된다. 이들 회로에는 저주파 잡음과 오프셋을 감소시키기 위한 correlated-double-sampling(CDS)와 chopper-stabilization(CHS) 기법이 적용되었다. 설계 결과 CVC는 150mV/g의 민감도와 0.15%의 비선형성을 갖는다. 설계된 <TEX>${\Sigma}{\Delta}$</TEX> 변조기는 입력전압 진폭이 100mV가 증가할 때, 출력의 듀티 싸이클은 10%씩 증가하며, 0.45%의 비선형성을 갖는다. 전체 회로의 민감도는 150mV/g이며, 전력소모는 5.6mW이다. 제안된 회로는 CMOS 0.35um 공정을 이용하여 설계하였고, 공급 전압은 3.3V이며, 동작 주파수는 2MHz이다. 설계된 칩의 크기는 PAD를 포함하여 <TEX>$0.96mm{\times}0.85mm$</TEX>이다. This paper presents a CMOS readout circuit for MEMS(Micro Electro Mechanical System) acceleration sensors. It consists of a MEMS accelerometer, a capacitance to voltage converter(CVC) and a second-order switched-capacitor <TEX>${\Sigma}{\Delta}$</TEX> modulator. Correlated-double-sampling(CDS) and chopper-stabilization(CHS) techniques are used in the CVC and <TEX>${\Sigma}{\Delta}$</TEX> modulator to reduce the low-frequency noise and DC offset. The sensitivity of the designed CVC is 150mV/g and its non-linearity is 0.15%. The duty cycle of the designed <TEX>${\Sigma}{\Delta}$</TEX> modulator output increases about 10% when the input voltage amplitude increases by 100mV, and the modulator's non-linearity is 0.45%. The total sensitivity is 150mV/g and the power consumption is 5.6mW. The proposed circuit is designed in a 0.35um CMOS process with a supply voltage of 3.3V and a operating frequency of 2MHz. The size of the designed chip including PADs is <TEX>$0.96mm{\times}0.85mm$</TEX>.

Design of Capacitance to Voltage Converter for Capacitive Sensor Transducer

Problem statement: The design of Capacitance to Voltage Converter (CVC) for capacitive sensor transducer was presented. The proposed design will reduce the size, power consumption and supply voltage of the circuit and can be used in high frequency band transducer. Approach: The design was implemented using the Operational amplifier (Op amp) and capacitive network. The circuit was simulated using the PSPICE model parameters based on standard 0.13 μm CMOS process. Results: The design was able to measure a wide range of capacitance variations for the capacitive transducer. The performance analysis of the design showed desirable performance parameters in terms of response, low power consumption and a linear output voltage within the wide range of capacitive transducer capacitance variation for the power supply voltage of 1.2 V was achieved. Conclusion/Recommendations: The output voltage of the circuit varied linearly with the variation of capacitive transducer capacitance variation. The improved converter was compact and robust for integration into capacitive measuring systems and suitable for use in environment that making use of higher frequency band.