Capacitance Ratio Research Articles

A Low-Profile Reconfigurable Wide Band BPF with RF-MEMS Switches for 5G/ Satellite Applications

A low-profile wide-band tunable semi-circular cavity BPF is designed and analyzed in this work. RF-MEMS switches were utilized on either side of the 50 Ω microstrip transmission lines to provide reconfigurability. BPF tunability is achieved when the two switches travel from upstate to downstate in an electrostatically activated shunt capacitive shunt type RF-MEMS switch. The switch has a capacitance ratio of 10 and operates at a transition time of 30 μS with an actuation voltage of 6.5 V to move it downward. This is suitable for 5G wireless communication applications (n77, n78, and n79) as well as C-band applications. Return loss of -22 dB is obtained at 3.7 GHz when the switch is in the ON state, while reflection co-efficient of -32 dB is obtained at 6.7 GHz when the switch is in the OFF state. When both switches are ON or OFF, a bandpass filter provides a 3GHz frequency shift. The frequency range where BPF is intended to operate, which is adjustable for various purposes, is 1–10 GHz. The characteristics of the switch were investigated by simulating its design in COMSOL Multiphysics and the outcomes were contrasted with theoretical computations. The adjustable properties of the BPF have been observed and shown using the HFSS v 13 tool.

Super-Lamination HZO/ZrO₂/HZO of Ferroelectric Memcapacitors With Morphotropic Phase Boundary (MPB) for High Capacitive Ratio and Non-Destructive Readout

Super-Lamination HZO/ZrO₂/HZO of Ferroelectric Memcapacitors With Morphotropic Phase Boundary (MPB) for High Capacitive Ratio and Non-Destructive Readout

High Memory Window, Dual‐Gate Amorphous InGaZnO Thin‐Film Transistor with Ferroelectric Gate Insulator

Ferroelectric (FE) hafnium zirconium oxide (HZO) thin‐film transistors (TFTs) are of increasing interest for next‐generation memory and computing applications. However, these devices face challenges in achieving a substantial memory window (MW). This report presents amorphous InGaZnO (a‐IGZO) ferroelectric–dielectric (FD), dual‐gate thin‐film transistors (DG‐TFTs) with FE‐HZO as a bottom gate insulator (GI) and SiO2 as a top GI. The ferroelectricity in HZO is confirmed through the grazing incidence X‐ray diffraction (GI‐XRD), capacitance, and polarization measurements. The FD‐DG TFT can increase the MW by tuning the threshold voltage (VTH) due to electrostatic coupling between the top gate (TG) and bottom gate (BG). The increase of MW at the TG driving is related to the coupling factor which is equal to the ratio of the equivalent capacitance of top to bottom gated transistors. During the bottom sweep, the FD‐DG‐TFT demonstrates an anticlockwise hysteresis with a MW of 4.98 V, a high ION/IOFF ratio of ≈106, and a steep subthreshold swing (SS) of 90 mV dec−1. On the contrary, MW of 12 V and SS of 140 mV dec−1 are observed for the top sweep operation. A thinner ferroelectric GI at BG TFT induces sufficient electrostatic coupling to cause a large VTH shift at TG driving, resulting in a boosted MW.

Thermosensitive double-membrane neurons and their network dynamics

Abstract Cell membrane of biological neurons has distinct geometric structure, and involvement of diffusive term is suitable to estimate the spatial effect of cell membrane on neural activities. The gradient field diversity between two sides of the cell membrane can be approached by using a double-layer membrane model for the neuron. Therefore, two capacitive variables and diffusive terms are used to investigate the neural activities of cell membrane, and the local kinetics is described by a functional circuit composed of two capacitors. The voltages for the two parallel capacitors describe the inner and outer membrane potentials, and the diffusive effect of ions is considered on the membrane surface. The results reveal that neural activities are relative to the capacitance ratio between the inside and outside of the membrane and diffusive coefficient. High-energy periodic external stimulation induces the target waves to spread uniformly, while low-energy chaotic stimulation results in wave fragmentation. Furthermore, when the capacitance ratio exhibits exponential growth under an adaptive control law, the resulting energy gradient within the network induces stable target waves. That is, energy distribution affects the wave propagation and pattern formation in the neuron. The result indicates that the spatial diffusive effect and capacitance diversity between outer and inner cell membranes are important for selection of firing patterns and signal processing during neural activities. This model is more suitable to estimate neural activities than using generic oscillator-like or map neurons without considering the spatial diffusive effect.

Accurate Technique for the Calibration of High-Voltage Capacitance and Dissipation Factor Bridges up to 1 kHz

This paper presents a comprehensive methodology for the precise calibration of high-voltage capacitance and dissipation factor (DF) bridges. The technique involves meticulous adjustments using a digital high-precision phase and ratio-measuring system to determine correction factors for DF and capacitance measurements. Unlike other methods that are limited to a narrow range, this approach allows calibration across the entire operational working spectrum of any bridge. While the method has been developed up to 1 kHz, its adaptability for future requirements is facilitated by the developed software. This method has been carried out by calibrating a highly accurate bridge for a capacitor ratio of up to 100, with DFs ranging from −0.01 to 0.01 and currents ranging from 0.1 mA to 1 A. Linear correction factors are established, with their accuracies being rigorously quantified. This methodology achieves expanded uncertainties as low as 3.5 µF/F (3.5 ppm) for capacitance and 2.2 × 10−⁶ for DFs, significantly enhancing measurement reliability across diverse high-voltage capacitor applications.

Dual redox centers in MnCo2O4 nanorod cathode for highly efficient capacitive deionization

Capacitive deionization (CDI) technology via faradic electrodes with active redox pairs has achieved tremendous success in desalination. However, the inner collaborative mechanisms of multi-redox centers in electrodes are rarely deep-analyzed. Thus, this work intensively investigated the inner enhanced mechanisms of multi-redox centers, starting from the dual-redox-based MnCo2O4 nanorod (MCO-NR) cathode in capacitive desalination. The electrochemical tests indicated a surface capacitive ratio of MCO-NR as high as 86 % when the scan rate was 100 mV s−1. Multi-dimensional CDI tests demonstrated that the highest capacity of MCO-NR could reach 61.78 mg g−1, with four theory models elaborating the electrosorption kinetics and maximum desalination capability. The refined ex-situ XPS measurements, carefully designed comparative experiments, and DFT calculations were used to analyze the Na+ (de)intercalation characteristics, the inner enhanced electrosorption mechanisms of dual redox centers, and the effects that the Mn redox center exerts on the MnCo2O4 structure. These results showed the superiority of dual- or multi-redox-center-based faradic capacitive desalination, providing a new perspective for designing high-property faradic electrode materials.

The Design, Simulation, and Parametric Optimization of an RF MEMS Variable Capacitor with an S-Shaped Beam

This study presents the design and simulation of an RF MEMS variable capacitor with a high tuning ratio and high linearity factor of capacitance–voltage response. An electrostatic torsion actuator with planar and non-planar structures is presented to obtain the high tuning ratio by avoiding the occurrence of pull-in point. In the proposed design, the capacitor plate is connected to the electrostatic actuators by using the s-shaped beam. The proposed design shows a 138% tuning ratio with the planar structure of the actuator and 167% tuning ratio by implementing the non-planar structure. A linearity factor of 99% is attained by adjusting the rates at which the capacitor plate rises as the actuation voltage increases and the rate at which the capacitance decreases as the plate rises. Parametric optimization of the design is performed by utilizing the finite element method (FEM) analysis and high-frequency structural simulator (HFSS) analysis to obtain an optimized high-tuning ratio RF MEMS varactor at low actuation voltage. S-parameters of the design are presented on HFSS, with a 50 ohm coplanar waveguide (CPW) serving as the transmission line. The proposed RF MEMS varactor can be utilized in tunable RF devices.

Electrical Performance Enhancement of 400 V Level Aluminum Solid Electrolytic Capacitors with Interface Modulation through Intervention of PVA

Poly(3,4‐ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS), a conductive polymer dispersion, is widely used in cathodes of solid electrolytic capacitors. However, it still suffers from performance limitations when used at high frequencies, and its withstand voltage must be improved. Herein, impregnation drying introduces a polyvinyl alcohol (PVA) coating onto alumina, which regulates the interface between the PEDOT:PSS cathode and alumina. The equivalent series resistance (ESR) of the capacitor is significantly reduced, whereas the withstand voltage is slightly improved. This study demonstrates that the presence of PVA enhances the wettability of PEDOT:PSS dispersions on alumina surfaces. Changes in the infrared peak positions of the OH and SO3H groups following the mixing of the PVA and PEDOT:PSS films, along with alterations in the thermal decomposition temperature, indicate the occurrence of crosslinking. Theoretical calculations demonstrate the presence of hydrogen bonds between the OH groups in PVA and the SO3H groups of PEDOT:PSS. Interface modulation effectively improves capacitor performance, as the capacitance ratio of capacitors with 400 V level withstand voltages increases from 97.35% to 98.85%, and the ESR at 100 kHz is significantly reduced by ≈40%. This study provides a valuable reference for the preparation of high‐performance solid electrolytic capacitors.

Advantages of a novel truncated cone DE-air generator in energy conversion

Abstract Harvesting energy from ambient environments such as vibrations is a feasible approach to selfpower low powered electric devices. T- he dielectric elastomer generator (DEG) is a type of novel electrostatic generator with superior vibration energy harvesting (EH) performance. On the basis of traditional DEGs, a new concept of dielectric elastomer (DE)-air generator (DEAG), which contains the air layer and the DE membrane (DEM) as a composite dielectric layer, is proposed in this paper for the first time. Inspired by a classical truncated cone DEG (TC-DEG) concept, the novel truncated cone DEAG (TC-DEAG) is designed and comprehensively studied. Compared with the TC-DEG, the proposed TC-DEAG provides the larger capacitance ratio, leading to superior electrical output. The energy conversion mechanisms of both the TC-DEG and the TC-DEAG under a regular linear reciprocating excitation are analyzed theoretically by deducing the deformation condition of the DEM and the electrical outputs. Through measuring the capacitance of the DEM under deformations and testing the output voltage of the fabricated generators, the proposed theoretical models and predictions are verified. Moreover, numerical simulations based on the verified theoretical model are conducted to reveal the influences of some important system parameters on the EH performances of both generators, providing guidelines for the performance improvement of the generators.

Effect of the Magnetic Field and Rotation on Peristaltic Flow of A Carreau Fluid in Asymmetric Channel with Porous Medium

In this paper, the instability of the Carreau fluid was discussed in the asymmetric channel with a porous medium in the presence of a changing magnetic field and rotation. The Carreau fluid behaves like a non-Newtonian fluid, where it was found that the rotation has an effect on the stability of the fluid. Numerical methods are used to solve the equations, such as the perturbation method. Assumptions are used to analyze the flow. The effect of Hartmann number (Ha), Darcy number (Da), material fluid (We), magnetic field (β), capacitance ratio (∅) and rotation are calculated(Ω)Numerical results were calculated using MATHEMATICA program

Gallium arsenide octave-bandwidth microwave voltage-controlled oscillator having discrete varicap

Modern reconfigurable communication systems demand microwave voltage-controlled oscillators (VCOs) possessing an octave-wide bandwidth. Many advanced applications require also a low phase noise and a low current consumption for such VCOs. To meet an octave-bandwidth specification in combination with a low phase noise and a low current consumption it is desirable to implement a microwave monolithic integrated circuit (MMIC) technology. In-house gallium arsenide (GaAs) MMIC technology is implemented to build VCOs in this work. At the same time, in order to achieve a high-Q wide frequency tuning range, we implemented also a discrete variable capacitance diode (varicap). The discrete varicap is stacked above MMIC oscillator chip. A vertical design structure of the discrete varicap guarantees a high overlap capacitance ratio (K>20) along with reduced affect of the parasitic reactance. A high overlap capacitance ratio is needed for an octave-wide frequency tuning, while reduced affect of the parasitic reactance increases Q-factor of the VCO resonator. Hence, a sequential integration of the discrete varicap over monolithic oscillator chip resolves referred tough challenges in the design of VCO. Integrated VCO is finally packaged as a surface-mount device (SMD). At that SMD ceramic package is sealed with the metal lid. The oscillator circuitry is based on the conventional negative resistance approach with a positive feedback realized by common-source capacitance. An active element of the oscillator is a pseudomorphic high electron-mobility transistor (pHEMT). The gate length of a transistor is 0.15 µm. The width of the gate varies from 240 µm to 360 µm depending on working frequencies of the VCO. The varicap is built on the GaAs epitaxial heterostructure having customized gradient doping profile with abrupt junction. Nonlinear behavioral model of the varicap is extracted from the diode measurements and is further used for VCO simulation. Two types of VCO have been designed, fabricated and tested. First (second) type of VCO provides a tuning range from 5 to 10 GHz (from 10 GHz to 20 GHz), respectively. The measurement results demonstrate an output power of 3.9 dBm; a current consumption of 30 mA at a supply voltage of 5 V; a phase noise of minus 90 dBc/Hz at 100 kHz offset (minus 85 dBc/Hz at 100 kHz offset) for the first (second) type of VCO, respectively.

ВПЛИВ ВЕЛИЧИНИ ЄМНОСТІ ПОСЛІДОВНОГО РЕЗОНАНСНОГО КОНТУРУ НА ПОТУЖНІСТЬ ЕЛЕКТРОТЕХНІЧНИХ СИСТЕМ РЕЗОНАНСНОГО ТИПУ ДЛЯ МОНІТОРИНГУ ІЗОЛЯЦІЇ ВИСОКОВОЛЬТНОГО ОБЛАДНАННЯ

It were analyzed the processes of charging the capacitive electro-technical storage (CES), which can be the electrical insulation of modern high -voltage equipment (in particular power cables) during the current monitoring of its techni-cal condition by the value of leakage currents when applying high voltage to insulation. The transformerless electro-technical system (ETS) of a resonance type, in which resonant inductive-capacitive circuit (ICС) with a high Q -factor carried out a multiple increase in AC voltage, was used to generate such voltage. Analytical expressions were obtained for the steady-state voltage on such CES and transient currents in the ETS circuit its charging. Simulation modeling of transient processes in the circuits of such ETS during CES charging was performed using the LTSpice software pack-age. It is shown that the dependences of the output voltage and current of the ETS on time, obtained by analytical ex-pressions, practically coincide with the results of simulation simulations. The influence of the ratio of the load capaci-tance and the resonant circuit capacitance on the relative load charging time and, accordingly, on the ETS power was studied. It was found that in order to increase the power of high -voltage transformerless ETS of the specified reso-nance type, it is necessary to increase the ratio of the CES capacity to the ICС capacity of the resonant circuit of the ETS. This approach can be used when using ETS with resonant ICCs to create powerful electric discharge installations (EDIs) for the implementation of technologies for obtaining electro-spark micro- and nanopowders with unique opera-tional properties. When creating powerful EDIs, it is suggested to use the value of the above-mentioned ratio at least 10. References 31, figures 5.

Rare earth doped bimetal hydroxide/multi-walled carbon nanotubes as composite electrodes to achieve high-energy-density asymmetric supercapacitors

A novel electrode material of Ni–Co bimetallic hydroxide composite multi-wall carbon nanotubes (La–NiCo LDH/MWCNTs/NF) doped with rare earth elements was prepared on nickel foam (NF) by a one-step hydrothermal method and doped with different concentrations of La3+ ions. The introduction of La3+ ions can increase the layer spacing of LDH materials. The acidification of MWCNTs on the surface of NF can also enhance the collection effect of NF. The synergistic effect of MWCNTs and La3+ ions further improves the specific capacitance of the material. At the current density of 1 A g−1, the maximum specific capacitance of the sample with 5 % La3+ ion concentration reaches 4396.0 F g−1, and the capacitance retention is 70.31 % after 3000 cycles of a single electrode. When assembled into a device, the device obtains a high energy density of 77.86 Wh kg−1 at a power density of 800.0 W kg−1. After assembling into an asymmetric supercapacitor, it has undergone 8000 cycles of performance testing, and the capacitance ratio is only reduced by 4.9 %. It shows good electrochemical cycle performance. This work provides a new way to study the doping of rare earth elements for supercapacitor materials.

Анализ влияния отклонений на нелинейность в гибридном RC-ЦАП

This paper is dedicated to the analysis of the effect of elements mismatch on the nonlinearity of N-bit hybrid segmented RC-digital-to-analog converter. In the structure of the hybrid digital-to-analog converter under consideration, a binary capacitive segment processes the most significant bits, whereas a unary resistive segment processes the least significant bits. Since the consi¬dered digital-to-analog converter is heterogenous, the elements of both segments differ by the type (resistors or capacitors) and area. This causes an optimal ratio of segments resolutions to shift in respect to the total DAC area minimization. Therefore, the goal of the current research is to obtain an expression for optimal segments resolutions in dependance on the ratio of unit capacitor and resistor areas. For this purpose, a parametric mathematical model of the considered converter has been developed in MATLAB. The elements arrays of both segments are influenced by random errors. The simulation of differential and integral nonlinearities has been carried out, which demonstrated a lower contribution of the resistive segment on nonlinearity, in contrast to the capacitive one. Besides, the increment of a capacitive segment resolution improves the yield of both nonlinearities.

1 V Tunable High-Quality Universal Filter Using Multiple-Input Operational Transconductance Amplifiers.

This paper presents a new multiple-input single-output voltage-mode universal filter employing four multiple-input operational transconductance amplifiers (MI-OTAs) and three grounded capacitors suitable for low-voltage low-frequency applications. The quality factor (Q) of the filter functions can be tuned by both the capacitance ratio and the transconductance ratio. The multiple inputs of the OTA are realized using the bulk-driven multiple-input MOS transistor technique. The MI-OTA-based filter can also offer many filtering functions without additional circuitry requirements, such as an inverting amplifier to generate an inverted input signal. The proposed filter can simultaneously realize low-pass, high-pass, band-pass, band-stop, and all-pass responses, covering both non-inverting and inverting transfer functions in a single topology. The natural frequency and the quality factors of all the filtering functions can be controlled independently. The natural frequency can also be electronically controlled by tuning the transconductances of the OTAs. The proposed filter uses a 1 V supply voltage, consumes 120 μW of power for a 5 μA setting current, offers 40 dB of dynamic range and has a third intermodulation distortion of -43.6 dB. The performances of the proposed circuit were simulated using a 0.18 μm TSMC CMOS process in the Cadence Virtuoso System Design Platform to confirm the performance of the topology.

A 206.4 dBc/Hz FoMT Class-F23 VCO using nonlinear-capacitance-transforming technique

—In this paper, a class-F23 VCO using nonlinear-capacitance transforming technique to simultaneously achieve low phase noise and a wide tuning range is proposed. The phase noise degradation due to the nonlinearity of the switched capacitor in the class-F23 oscillator is analyzed and quantitatively derived. The phase noise contributed by the nonlinear capacitance can be suppressed by using the proposed nonlinear-capacitance transformation technique. In order to achieve low phase noise over a wide bandwidth, the asymmetric-toggling method is utilized to achieve optimal capacitance ratios across the entire frequency range. Implemented in a 40-nm CMOS process, the proposed oscillator exhibits 41.2 % tuning range from 2.58 GHz to 3.92 GHz while consuming 13.8 mW–14.9 mW power dissipation. The phase noises at 2.58 GHz and 3.92 GHz oscillation frequencies are −136.4 dBc/Hz and −129.6 dBc/Hz at 1-MHz offset. The minimum phase noise is −157.2 dBc/Hz at 10 MHz offset, corresponding to an FoM of 194.1 dBc/Hz and FoMT of 206.4 dBc/Hz.

Ferroelectric capacitors and field-effect transistors as in-memory computing elements for machine learning workloads

This study discusses the feasibility of Ferroelectric Capacitors (FeCaps) and Ferroelectric Field-Effect Transistors (FeFETs) as In-Memory Computing (IMC) elements to accelerate machine learning (ML) workloads. We conducted an exploration of device fabrication and proposed system-algorithm co-design to boost performance. A novel FeCap device, incorporating an interfacial layer (IL) and Hf0.5Zr0.5O2\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\ ext {Hf}_{0.5}\ ext {Zr}_{0.5}\ ext {O}_2$$\\end{document} (HZO), ensures a reduction in operating voltage and enhances HZO scaling while being compatible with CMOS circuits. The IL also enriches ferroelectricity and retention properties. When integrated into crossbar arrays, FeCaps and FeFETs demonstrate their effectiveness as IMC components, eliminating sneak paths and enabling selector-less operation, leading to notable improvements in energy efficiency and area utilization. However, it is worth noting that limited capacitance ratios in FeCaps introduced errors in multiply-and-accumulate (MAC) computations. The proposed co-design approach helps in mitigating these errors and achieves high accuracy in classifying the CIFAR-10 dataset, elevating it from a baseline of 10% to 81.7%. FeFETs in crossbars, with a higher on-off ratio, outperform FeCaps, and our proposed charge-based sensing scheme achieved at least an order of magnitude reduction in power consumption, compared to prevalent current-based methods.

Pore structure and oxygen content design of amorphous carbon toward a durable anode for potassium/sodium‐ion batteries

AbstractBoth sodium‐ion batteries (SIBs) and potassium‐ion batteries (PIBs) are considered as promising candidates in grid‐level energy storage devices. Unfortunately, the larger ionic radii of K+ and Na+ induce poor diffusion kinetics and cycling stability of carbon anode materials. Pore structure regulation is an ideal strategy to promote the diffusion kinetics and cyclic stability of carbon materials by facilitating electrolyte infiltration, increasing the transport channels, and alleviating the volume change. However, traditional pore‐forming agent‐assisted methods considerably increase the difficulty of synthesis and limit practical applications of porous carbon materials. Herein, porous carbon materials (Ca‐PC/Na‐PC/K‐PC) with different pore structures have been prepared with gluconates as the precursors, and the amorphous structure, abundant micropores, and oxygen‐doping active sites endow the Ca‐PC anode with excellent potassium and sodium storage performance. For PIBs, the capacitive contribution ratio of Ca‐PC is 82% at 5.0 mV s−1 due to the introduction of micropores and high oxygen‐doping content, while a high reversible capacity of 121.4 mAh g−1 can be reached at 5 A g−1 after 2000 cycles. For SIBs, stable sodium storage capacity of 101.4 mAh g−1 can be achieved at 2 A g−1 after 8000 cycles with a very low decay rate of 0.65% for per cycle. This work may provide an avenue for the application of porous carbon materials in the energy storage field.

Propagation characteristics of elastic longitudinal wave in a piezoelectric semiconductor metamaterial rod and its tuning

Elastic metamaterial structures have many distinct wave properties such as band gap structure and topological phase inversion. The coexistence and interaction of piezoelectricity and semiconductor behavior in piezoelectric semiconductor (PS) materials endow metamaterials with some new physical effects. We investigate the propagation characteristics of elastic longitudinal waves in a metamaterial rod made of n-type PS material and piezoelectric (PE) dielectric material. Based on one-dimensional rod model, we present the transfer matrixes for the PS and PE phases as well as the interfacial transfer matrix of unit cell. The analytical dispersion relations of the considered PS-PE metamaterial rod are obtained by utilizing Bloch's theorem. Numerical results show that band gap structures of the metamaterial rod are dependent on the initial electron concentration, length ratio of PE phase, interfacial condition, and capacitor connected with the PE phase. The selection of certain initial electron concentration, length ratio of PE phase, and capacitor can lead to the appearance of topological phase inversion, highlighting the potential for controlling and manipulating the wave propagation properties of PS metamaterial structures. This paper provides a theoretical guidance on the development of smart devices based on PS metamaterial structures. The novel combination of piezoelectricity and semiconductor behavior in these materials opens up new avenues for designing and engineering advanced devices with tailored wave properties and functionalities.

Automated design flow for synthesizable ADPLL: From specification to GDS

We propose an automated design flow for an all-digital phase-locked loop (ADPLL) that selects and implements a PLL layout that satisfies user given input specifications using place-and-route (PnR) tools within 1.2 h. The all-digital architecture enables the use of a theory-based frequency domain model for predicting the output specifications once the oscillator performance is characterized. The cell-based digitally controlled oscillator (DCO) is modeled by extracting the PDK and cell specific constants that characterize the effective current to capacitance ratio from only 3 sets of SPICE simulations. The constants are then used to predict the analog performance with an analytical model, which shows an error rate less than 1.5 % for estimating frequency range and power consumption. The generator guides the user to a feasible set of specifications using the analytical model by providing the achievable range of the failed specification. As design examples, 8 generated PLL designs and their post-parasitic performances are compared to input specifications, including one measurement result from a fabricated chip in 65 nm CMOS process.