Capacitance Multiplier Research Articles

VCII‐Based Immittance Simulators: Generalized Parallel Configurations

ABSTRACTIn this paper, four new generalized configurations of grounded parallel‐type immittance simulators are proposed. These circuits implement parallel resistor–inductor (RL), parallel resistor–capacitor (RC), parallel capacitor–frequency‐dependent negative resistance (CD), and capacitance multiplier configurations utilizing only two second‐generation voltage conveyors (VCII±) as active elements along with three impedances, without the need for specific matching conditions. The applicability of the proposed parallel RL and capacitance multiplier configurations as a second‐order high‐pass filter (HPF) and a first‐order low‐pass filter (LPF), respectively, is also demonstrated. These applications illustrate the versatility and utility of the proposed structures. Frequency, transient, and Monte Carlo analysis utilizing the CMOS VCII± in the SPICE simulation tool have also been performed to validate the feasibility of the presented circuits. Further validation is carried out through layout design in Cadence Virtuoso, employing 0.18‐μm CMOS technology. Both presimulation and postsimulation results are presented for a thorough assessment of the proposed circuits. Also, the claimed theory is verified by experimental results based on the VCII implementation with commercially available IC AD844.

Electronically Tunable Grounded and Floating Capacitance Multipliers Using a Single Active Element

A capacitance multiplier is an active circuit designed specifically to increase the capacitance of a passive capacitor to a significantly higher capacitance level. In this paper, the use of a voltage differencing differential difference amplifier (VDDDA), an electronically controllable active device for designing grounded and floating capacitance multipliers, is proposed. The capacitance multipliers proposed in this study are extremely simple and consist of a VDDDA, a resistor, and a capacitor. The multiplication factor (Kc) can be electronically controlled by adjusting the external bias current (IB). It offers an easy way of controlling it by utilizing a microcontroller for modern analog signal processing systems. The multiplication factor has the potential to be adjusted to a value that is either less than or greater than one, hence widening the variety of uses. The grounded capacitance multiplier can be easily transformed into a floating one by utilizing Zc-VDDDA. PSpice simulation and experimentation with a VDDDA realized from commercially available integrated circuits were used to test the performance of the proposed capacitance multipliers. The multiplication factor is electronically adjustable, ranging in approximation from 0.56 to 13.94. The operating frequency range is approximately three frequency decades. The realization of the lagging and leading phase shifters using the proposed capacitance multiplier is also examined and proven. The results reveal that the lagging and leading phase shifts are electronically tuned via the multiplication factor of the proposed capacitance multipliers.

A New CMOS FTFNDITA Implementation and Its Application

ABSTRACT This research article presents a new design of a CMOS analog building block, termed a Four Terminal Floating Nullor Differential Input Transconductance Amplifier (FTFNDITA). This new analog building block can operate up to the MHz range and offers low-power dissipation circuitry. The proposed FTFNDITA works with ± 1.65 V power supply. Moreover, a ICs-based FTFNDITA is also developed using an off-self commercially available Current Feedback Operational Amplifier (CFOA) as IC AD844 and Operational Transconductance Amplifier (OTA) as IC LM13700 or IC CA3080. To extend the application perspective of the proposed FTFNDITA blocks, a few fundamental analog signal processing circuits like the design of Floating Inductor Simulator (FIS), First-Order Low-Pass Filter (FLPF), Floating Capacitance Multiplier (FCM), and its extension for active filter design, are incorporated. In addition, a non-ideality investigation is also performed to test the deviation between the ideal and practical design. Finally, PSPICE and experimental verifications are observed to validate the functionality of FTFNDITA.

Design of Lossless Negative Capacitance Multiplier Employing a Single Active Element

In this paper, a new negative lossless grounded capacitance multiplier (GCM) circuit based on a Current Feedback Operational Amplifier (CFOA) is presented. The proposed circuit includes a single CFOA, four resistors, and a grounded capacitor. In order to reduce the power consumption, the internal structure of the CFOA is realized with dynamic threshold-voltage MOSFET (DTMOS) transistors. The effects of parasitic components on the operating frequency range of the proposed circuit are investigated. The simulation results were obtained with the SPICE program using 0.13 µm IBM CMOS technology parameters. The total power consumption of the circuit was 1.6 mW. The functionality of the circuit is provided by the capacitance cancellation circuit. PVT (Process, Voltage, Temperature) analyses were performed to verify the robustness of the proposed circuit. An experimental study is provided to verify the operability of the proposed negative lossless GCM using commercially available integrated circuits (ICs).

A current mode capacitance multiplier employing a single active element based on Arbel-Goldminz cells for low frequency applications

In this work, a capacitor multiplier based on a Multiple Output-Voltage Difference Transconductance Amplifier (MO-VDTA) is built by using Arbel-Goldminz cells with extensive performance analysis. Considering the large chip area occupation of capacitors, capacitor multipliers are one of the most required analog building blocks in most of low frequency applications. In this respect, the obtained capacitor multiplier is tested in a 2nd order low-pass filter by changing the cut-off frequency from 2 kHz to around 12.4 kHz. The multiplication factor (denoted as “k”) of the proposed architecture can be adjusted electronically from 120 to 750 for approximately two decades, while the structure contains only a single active element with a base capacitance. Additionally, the multiplication factor can be safely increased by using additional transconductance stages in the MO-VDTA active block. In the performance analysis, post-layout results are provided in conjunction with process corners, Monte-Carlo analyses and experimental verifications on the basis of commercial off-the-shelf elements such as AD844 and LM13700s.

A new ultra-low power wide tunable capacitance multiplier circuit in subthreshold region for biomedical applications

Implementing large capacitors in integrated circuits demands an occupation of a relatively significant large silicon area on-chip, which strictly limits the capability of the physical implementation of low-frequency integrated circuits that mostly require high capacitance values to provide large time-constants. Capacitance multipliers have been proposed to overcome this issue to realize high-value active capacitances in a small chip area. This paper proposes a new current-mode ultra-low power capacitance multiplier based on the floating capacitance Super Flipped Current Follower (SFCF) circuit which employs two AB class cascaded stages. The main novel idea behind the proposed circuit is combining the cross-coupling Quasi-Floating Gate (QFG) with the class-AB techniques and employing the Super Flipped Current Follower (SFCF) circuit, to enhance the adjustment efficiency ratio (M) factor, while also achieving a high scaling factor “K”. As a result, the proposed circuit achieves higher K value at the lower power and chip size area costs, while providing better adjustment efficiency ratio (M), which realizes a better “capacitance adjustability-power” trade-off. The proposed circuit provides other advantages such as: wide electronic tunability of scaling factor K, large Parallel Load Resistance (PLR) value, small value of Equivalent Series Resistance (ESR), relatively small chip size area, and a high ratio of adjustment efficiency (M). The total power consumption of the proposed circuit is obtained as 101 nW, using a base capacitance (Cb) of 1 pF, which leads to the realization of a maximum achievable equivalent capacitance (Ceq) of 1604 pF. In addition, the performance of the proposed tunable capacitance multiplier is examined in the realization of a wide-tunable low-pass filter structure. Furthermore, the performance robustness of the proposed circuit is investigated by the Monte-Carlo and PVT analyses in different technology corners, which justify the good performance of the proposed circuit that makes it a proper candidate to be used in ultra-low power biomedical signal processing.

A voltage mode grounded capacitance multiplier with widely tunable gain for ultra-low cutoff frequency filter.

A voltage mode capacitance multiplier for ultra-low frequency physiological signal processing is designed with a circuit model. With the proposed multiplier, a filter can achieve a cutoff frequency of 12 mHz with a 1 pF basic capacitance and a 10 kΩ resistor. The corresponding multiplication factor will be 1.35 × 109. By changing the controlling terminal, the multiplication factor can be widely tuned from 1950 to 1.35 × 109 and the corresponding filter cutoff frequency will be from 12 mHz to 8.15 kHz. According to the circuit model, to further increase the multiplication factor to decrease the chip area, more multiplication stages can be added to the feedback loop.

Consideration of Integrated Low-Frequency Low-Pass Notch Filter Employing CCII Based Capacitance Multipliers

Consideration of Integrated Low-Frequency Low-Pass Notch Filter Employing CCII Based Capacitance Multipliers

Lossless Grounded Capacitance Multiplier Based On Two CFOAs

A new lossless grounded capacitance multiplier (GCM) based on two current-feedback operational amplifiers (CFOAs) is proposed. The proposed circuit is built with a least number of passive elements. The capacitor is selected as grounded in the proposed circuit, while one resistor is grounded and the other is floating. The proposed GCM has low power consumption and a very large multiplying factor. The passive element matching conditions are not necessary for the designed GCM. The SPICE program is used for the simulations, and all the simulations are performed with 0.18µm CMOS technology parameters. The simulation results verify the ideal results from 10Hz to 15MHz. Further, the designed GCM is tested in the application circuit, which is a second-order passive filter. The experiments of the desgined GCM are achieved by using AD844s instead of CFOAs.

Two inverting CFOA-Based lossless floating immittance simulator

Inverting current feedback operational amplifier (ICFOA)-based lossless floating immittance simulator (FIS) is introduced in this manuscript. In the proposed FIS, floating capacitance multiplier (FCM), simulated floating inductor (SFI), and floating frequency-dependent negative resistor (FFDNR) can be obtained with selections of the passive elements. The proposed FIS is realized with a minimum number of passive elements. The proposed FIS is not suffered from any resistor and/or capacitor matching conditions; nevertheless, all the passive elements are chosen as floating. All the simulations of the FCM, SFI, and FFDNR are made by using the SPICE program in which 0.18 µm CMOS technology parameters are utilized. As an application example, the second-order passive band-pass filter is given for the FCM and SFI. Simulation results confirm the ideal results between about 5 Hz and 2 MHz for the FCM, between approximately 200 Hz and 5 MHz for the SFI, and between about 50 kHz and 13 MHz for the FFDNR. The proposed circuit has 1.49 mW power dissipation. In addition, the experiments of the proposed circuit and application are achieved by using AD844s instead of the ICFOAs.

Floating parallel lossy inductance, parallel lossy capacitance, parallel C‐D, and lossless capacitance multiplier circuits using current feedback operational amplifiers

SummaryA new synthetic floating simulator topology is proposed which realizes lossy parallel inductance (R‐L), lossy parallel capacitance (R‐C), lossy parallel C‐D, and lossless floating capacitance multiplier (FCM) circuits using only three current feedback operational amplifiers (CFOA) as active elements and three impedances. In all the presented circuits, the value of L, C, and D is independently controllable through a single resistance without requiring any matching condition for passive elements. A novel feature of the proposed circuit involves a straightforward adjustment in the CFOA connections, allowing the circuit to function as either a floating lossless immittance simulator or a floating series‐type lossy immittance simulator. Various application examples of the presented circuits such as lead compensator, lag compensator, first‐order high‐pass filter, and fourth‐order Butterworth filter are also given to justify the theoretical analysis. To validate the workability of the proposed circuits, several analyses are conducted, including frequency analysis, transient analysis, Monte‐Carlo analysis, and temperature analysis, using the macro‐model of AD844 in the SPICE simulation tool. Experimental results of the parallel R‐L simulator and application examples are also provided using commercially available IC AD844‐type integrated CFOAs.

Design and Implementation of High-Performance Power-Efficient Multiple-Output Class-AB Current Mirror For Capacitance Multiplier and Precision Rectifiers

The development of high-efficiency capacitance multipliers and precision rectifiers for VLSI (Very Large-Scale Integration) systems is examined in this work, with a focus on low voltage operation. The major goal is to reduce supply voltage in order to consume energy as little as possible. It has been successfully created for the capacitance multiplier to work properly even with extremely low voltage supply, as low as 0.25 V. Class-AB current mirrors, which are renowned for their outstanding current efficiency, are used in the design. Experimental measurements were made on a 180-nm CMOS-based capacitance multiplier that obtained a multiplication factor of 11 in order to assess performance. The same class-AB current mirrors were also used in the same CMOS technology to construct low-voltage precision rectifiers. Over a hundred times more output current than quiescent current is produced by these rectifiers. Notably, both circuits function with 0.25 V supply and dissipate static power at a rate of only 100 nW. The work shows that low-voltage designs and class-AB current mirrors can be used to produce great performance and efficient power usage in VLSI systems.

Novel Lossless Positive-/Negative-Grounded Capacitance Multipliers Using VCII

In the presented research, the second-generation voltage conveyor (VCII) is used in the design of active capacitance multipliers. In this paper, three positive and one negative lossless grounded capacitance multipliers (GCMs) are designed. All of these GCMs are designed using two VCIIs, one capacitor, and two resistors. There is no need for any passive component matching to implement a GCM. The multiplication factor of GCMs can be set/varied by changing the values of two resistances as per requirement. Considering nonideal constraints, GCMs are analysed mathematically to evaluate the effect of nonideal current and voltage transfer gains on the performance of the proposed GCMs. Also, parasitic analysis is conducted to study the effect of VCII node impedance on the performance of the presented GCMs. The simulation analysis is performed using Cadence Virtuoso in 0.18 µm Silterra Malaysia process design kit (PDK). Additionally, the macro-model of commercially available integrated circuit, AD844, is used to design the proposed GCM-2 to further prove the theoretical findings.

Single current follower differential input transconductance amplifier based grounded lossy capacitance multiplier with large multiplication factor

AbstractIn this paper, a new lossy capacitance multiplier (CM) circuit using a single current follower differential input transconductance amplifier (CFDITA), one resistor and one capacitor (virtually grounded) is presented. The proposed circuit does not require any passive component matching constraints and has independently controllable equivalent capacitance with a multiplication factor up to 7102. Both ideal and non‐ideal analyses of the proposed CM circuit are carried out and compared. The performance of the proposed CM circuit is validated using a CMOS CFDITA and its validity is supported by various analyses including frequency analysis, transient analysis, Monte‐Carlo analysis and temperature analysis. The workability of the proposed circuit is also tested using layout design, and its pre and post‐simulated results are appended. The results are further confirmed with experimental results using the AD844 and LM13700 ICs with CFDITA implementation.

ZVS–ZCS High Step-Up/Step-Down Isolated Bidirectional DC–DC Converter for DC Microgrid

A soft-switched isolated bidirectional dc–dc converter is proposed for distributed generation systems. Dual coupled inductor based flyback energy conversion circuit achieves high voltage step-up/down ratio and high efficiency at lowered duty cycle and, attributes the galvanic isolation. Active switch based capacitor multiplier cell appreciably reduces voltage stresses on low-voltage (LV) and high-voltage (HV) stage MOSFETs, thereby allowing low voltage rating devices(small <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>ds</i>(ON)</sub> ). Active-voltage-clamping type circuit extensively suppresses the voltage spikes across LV-switches caused by leakage inductance. Indeed, this clamp circuitry is formed without any additional switches/diodes, thus reduces clamp device count. By availing of quasi–resonance, thus without needing the HV stage snubber, switching voltage spikes are substantially alleviated. Further, this clamp along with quasi–resonance achieves zero-voltage (ZVS) and zero-current (ZCS) switching, over wide load range, for all switches in both step-up and step-down operations. Reduced voltage stresses, minimized clamp device count, diminished conduction losses and bidirectional soft-switching performance collectively enhances the efficiency. A 600 –W laboratory built set-up working at 75 kHz verifies the viability of the design concept. Measured peak efficiencies in boost and buck stages are 96.65% and 96.58%, respectively.

Analog interface based on capacitance multiplier for capacitive sensors and application to evaluate the quality of oils

&lt;abstract&gt;&lt;p&gt;Currently, interdigital capacitive (IDC) sensors are widely used in science, industry and technology. To measure the changes in capacitance in these sensors, many methods such as differentiation, phase delay between two signals, capacitor charging/discharging, oscillators and switching circuits have been proposed. These techniques often use high frequencies and high complexity to measure small capacitance changes of fF or aF with high sensitivity. An analog interface based on a capacitance multiplier for capacitive sensors is presented. This study includes analysis of the interface error factors, such as the error due to the components of the capacitance multiplier, parasitic capacitances, transient effects and non-ideal parameters of OpAmp. A design approach based on an IDC sensor to measure the quality of edible oils is presented and implemented. The quality relates to the total polar compounds (TPC) and consequently to relative electrical permittivity &lt;inline-formula&gt;&lt;tex-math id="M1"&gt;\begin{document}$ {\varepsilon }_{r} $\end{document}&lt;/tex-math&gt;&lt;/inline-formula&gt; of the oils. A measurement system has been implemented to measure the capacitance of the IDC sensor, which depended on &lt;inline-formula&gt;&lt;tex-math id="M2"&gt;\begin{document}$ {\varepsilon }_{r} $\end{document}&lt;/tex-math&gt;&lt;/inline-formula&gt;. The simulation and experimental results showed that, for a capacitance multiplication factor equal to 1000, changes of 3.3 µs/100 fF can be achieved with an acceptable level of noise, which can be easily measured by a microcontroller.&lt;/p&gt;&lt;/abstract&gt;

A linearly/electronically controllable high gain VDGA and its applications

Since the transconductance gains of an active building block namely voltage differencing gain amplifier (VDGA) is directly proportional to nonlinear (square root) function of external DC bias currents, affecting the narrow range tunability and low transconductance gains. This article aims to introduce a high gain VDGA by using CMOS current squaring circuits biasing in each transconductance cell. It offers high transconductance gains, wide range of tunability, linearity of controllability, larger input voltage range and nearly infinite input impedance. The proposed circuit was designed using a 0.18 µm CMOS transistors technology. The test was performed using PSpice program, it is consistent with the theoretical expectation. The total power consumption is 2.9 mW at ±1.5 V power supply. Even its power consumption is more than about 3 times of their previously proposed VDGAs, the figure of merit (FOM) of the proposed VDGA is much better than that of the previously proposed VDGAs (about 10 times). Additionally, the applications of the proposed VDGA as a capacitance multiplier, current multiplier/divider, summing amplifier, independently/electronically tunable multifunction filter, precision half-wave and full-wave rectifiers are included to insist the workability of the proposed VDGA.

Biyomedikal Uygulamalar için Kapasite Çarpıcı Kullanan Elektronik Olarak Ayarlanabilen Düşük Güçlü Alçak Geçiren Süzgeç

In this work, a novel 0.9nW low pass filter is proposed using 0.18µm TSMC technology in Cadence environment to reject unwanted signals of biomedical applications. Active RC filter is designed with a new capacitor multiplier implementation providing high multiplication factor along with low power consumption. The designed circuit operates with ±0.3V supply voltages with DTMOS technique. At the same time, the power consumption of the proposed circuit is very low that can be implemented in implantable devices. The bandwidth of the designed filter is adjustable between 500mHz and 65Hz. In terms of Figure of Merit, the proposed filter outperforms the recommended circuits in the literature.

CFOA-based floating frequency dependent negative resistor, floating capacitance multiplier, and simulated floating inductor

This paper introduces a new floating simulator circuit suitable for realizing a floating frequency dependent negative resistor (FFDNR) or a floating capacitance multiplier (FCM) with selections of the passive elements. In addition, a new circuit for realizing a simulated floating inductor (SFI) is introduced. The introduced FFDNR, FCM, and SFI use three current feedback operational amplifiers. The introduced FFDNR and FCM include a canonical number of passive components without any matching requirements, while the SFI contains three resistors and a grounded capacitor with a single resistive matching condition. Voltage-mode band-pass, low-pass, and notch filters are given as application examples.

New negative‐grounded capacitance multiplier circuits

SummaryIn this communication, three new negative‐grounded capacitance multiplier (NGCM) circuits employing a single current feedback operational amplifier (CFOA), two resistors, and a grounded capacitor (which is most suitable for parasitic absorption and also IC implementation point of view) are investigated. No matching constraints are required for any of the proposed circuit realizations. Out of the three proposed circuits, multiplication factor of one of the capacitance multiplier can be controlled electronically as the controlling resistor is grounded, which can easily be replaced by a voltage‐controlled resistor (VCR). Error analysis of the proposed NGCMs has been carried out, and the results have been compared with those obtained from ideal analysis. To substantiate the feasibility of the proposed circuits, macro model of CFOA has been used, and the simulations have been performed in Personal Simulation Program with Integrated Circuit Emphasis (PSPICE). Simulation results for frequency analysis, Monte‐Carlo analysis, and temperature analysis have been included for the theoretical justification. Noise analysis and power supply rejection ratio analysis have also been carried out for the proposed circuits. The multiplication factors of the proposed NGCMs have been obtained up to a maximum value of 2001. The impedance and phase of the proposed NGCM structures are insensitive with temperature. The functionality of the proposed structures has also been validated experimentally using commercially available IC AD844‐type CFOA.