Capacitance Equivalent Oxide Thickness Research Articles

Optimization of SiGe interface properties with ozone oxidation and a stacked HfO2/Al2O3 dielectric for a SiGe channel FinFET transistor

In this paper, the optimization of SiGe interface properties for the SiGe channel fin field effect transistor (FinFET) transistor is explored in detail. First, optimal low-temperature ozone oxidation at 300 °C for 30 min was confirmed based on Al2O3/Si0.7Ge0.3 metal-oxide-semiconductor (MOS) capacitors. This is because a higher oxidation temperature and a longer oxidation time can suppress the formation of GeO X in the interface layer (IL) and significantly improve the interface state density (D it). Moreover, compared with the Al2O3 sample, the HfO2 sample can obtain a thinner capacitance equivalent oxide thickness (CET), but it is more vulnerable to deterioration of Si0.7Ge0.3 interface properties because the GeO X in the IL is more likely to diffuse into the HfO2 layer. To further optimize the D it and CET of the Si0.7Ge0.3 MOS capacitor simultaneously, a stacked HfO2/Al2O3 dielectric is proposed. Compared with the HfO2 sample, its frequency dispersion characteristics and D it have been improved significantly, as the thin Al2O3 layer prevents the diffusion of GeO X to the HfO2 layer and controls the growth of GeO X . Therefore, a high-quality Si0.7Ge0.3 interface property optimization technology is realized via the development of a low-temperature ozone oxidation (300 °C, 30 min) method combined with a stacked HfO2/Al2O3 dielectric. In addition, a Si0.7Ge0.3 FinFET utilizing this newly developed interface property optimization scheme is successfully prepared. Its excellent subthreshold swing performance indicates that good interface quality of the Si0.7Ge0.3 is obtained. The above results prove that this newly developed interface property optimization scheme is a practical technology for high-mobility SiGe FinFET.

Group IV Transition Metal (M = Zr, Hf) Precursors for High-κ Metal Oxide Thin Films.

This paper describes the synthesis of eight novel zirconium and hafnium complexes containing N-alkoxy carboxamidate-type ligands, as potential precursors for metal oxides and atomic layer deposition (ALD) for HfO2. A series of ligands, viz., N-ethoxy-2,2-dimethylpropanamide (edpaH), N-ethoxy-2-methylpropanamide (empaH), and N-methoxy-2,2-dimethylpropanamide (mdpaH), were used to afford complexes Zr(edpa)4 (1), Hf(edpa)4 (2), Zr(empa)4 (3), Hf(empa)4 (4), Zr(mdpa)4 (5), Hf(mdpa)4 (6), ZrCp(edpa)3 (7), and HfCp(edpa)3 (8). Thermogravimetric analysis curves assessed for the evaporation characteristics of complexes 1-8 revealed single-step weight losses with low residues, except for the mdpa-containing complexes. Single-crystal X-ray diffraction studies of 1, 2, 5, and 6 revealed that all the complexes have monomeric molecular structures, with the central metal ion surrounded by eight oxygen atoms from the four bidentate alkoxyalkoxide ligands. Among the complexes prepared, 8 exhibited a low melting point (64 °C), good volatility (1 Torr at 112 °C), high thermal stability, and excellent endurance over 6 weeks at 120 °C. Therefore, an ALD process for the growth of HfO2 was developed using HfCp(edpa)3 (8) as a novel precursor. Furthermore, the HfO2 film exhibited a low capacitance equivalent oxide thickness of ∼1.5 nm, with Jg as low as ∼3 × 10-4 A/cm2 at Vg -1 V in a metal-insulator-semiconductor capacitor (Au/HfO2/p-Si).

Electrical properties of the HfO2/Al2O3 dielectrics stacked using single- and dual-temperature atomic-layer deposition processes on In0.53Ga0.47As

For sequential stacking of an Al2O3 passivation layer and a main HfO2 gate dielectric layer on In0.53Ga0.47As, we used single- and dual-temperature atomic-layer deposition processes, and systematically compared their effects on the dielectric-related electrical properties. When the deposition of Al2O3 passivation layer (approximately 0.7−0.8 nm) took place at relatively low temperatures of 100 °C, an increase in the subsequent deposition temperature for HfO2 (from 100 to 300 °C) assisted in decreasing both capacitance-equivalent oxide thickness and the number of bulk-related traps. However, the valuable reduction in both near-interface defect density and leakage current through the low-temperature Al2O3 passivation approach was monotonically lessened with an increase in the process temperature for the subsequent HfO2 deposition, which suggests the need for a careful optimization of a thermal budget for the dual-temperature process.

(Invited) Advanced Replacement High-K/Metal Gate Stack Engineering for High-Performance Strained Silicon-Germanium Finfets with High Ge Content

Strain engineering for pFETs has been conventionally enabled utilizing embedded SiGe in the source/drain regions to continuously boost the transistor current drive and transconductance [1]. Historically, for planar technologies, transconductance was monotonically improved by advancing the technology generations. However, this trend for transconductance, when properly normalized to the effective device width (fin perimeter) is no longer observed when FinFETs were introduced to the mainstream CMOS to improve the short channel effects for sub 30nm gate lengths [2]. The FinFET transconductance saturation or drop be attributed to ineffectiveness of the embedded SiGe stressors (in spite of higher mobility near-(110) surfaces) and/or increased contribution of the S/D resistance as the contacted gate pitch size aggressively scales down. Unless there is a strong and reliable method to externally apply gigantic strain to the Si fin channel, using strained SiGe (s-SiGe) channel, with built-in uniaxial compression, is a strong option to overcome this issue. In fact, SiGe has been utilized in CMOS industry as a knob to control the threshold voltage (Vth) and in part to boost the pFET reliability and transport [3]. Moreover, introduction of SiGe channel for planar pFET has improved reliability, resulting in further Capacitance-Equivalent-oxide-Thickness (CET) scaling over Si. For s-Si1-xGex FinFETs, choice of Ge content (x) is not trivial. Adding more Ge can ideally build in more channel stress resulting increased hole mobility and current drive. However, epitaxial-defect-driven fin height control due to the critical thickness constraints, process thermal budget, bandgap reduction and gate-induced drain leakage (GIDL) control remain challenging. In particular, High-Ge-Content (HGC) s-SiGe FinFETs are of great interest for two reasons, from the transport point of view: First, very high level of strain (close to 3GPa) can be achieved when lattice matched to Si [4]. Second, if strain-relaxed buffer (SRB) SiGe with moderate Ge % is used to tensily strain Si nFET, higher Ge is required to compressively strain the pFET [5]. The GIDL issue can be mitigated by operating the high-performance (HP) device at a lower VDD, i.e. below 0.6V, in line with logic roadmap [4]. Controlling the HFIN, to be competitive with the state-of-the-art Si FinFETs, remains challenging. Above all, a major challenge is associated with the gate stack and interface trap control which is more pronounced in HGC SiGe than Si and pure Ge. In this talk, key process details to enable relatively tall fins and optimized replacement high-k metal gate (RMG) stacks in high-Ge-content SiGe will be discussed and their impact on key device characteristics will be presented. In particular, we review our recent advancement to achieve optimized RMG IL and passivation [6], high hole mobility and record performing short channel pMOS FinFETs. In additions, a metal gate work-function tuning solution will be presented utilizing an ultra-thin replacement metal-gate scheme to achieve target high-performance off current down to 15nm gate lengths.

Electrical properties of HfO2/Al2O3 dielectrics fabricated on In0.53Ga0.47As by using atomic layer deposition at low temperatures (100 - 200 ◦C)

The electrical properties of HfO2/Al2O3 stacked dielectrics on n-type In0.53Ga0.47As were investigated as a function of the atomic layer deposition (ALD) temperature, particularly within the low temperature range from 100 to 200° C. Although the capacitance equivalent oxide thickness increased due to decreases in the dielectric constants of the HfO2 and the Al2O3 films, lowering the ALD temperature to 100° C improved the interface-related electrical characteristics, such as the interface state density and frequency dispersion under accumulation. In particular, a significant reduction in the leakage current was achieved at a similar physical thickness under substrate electron injection conditions, which was probably due to the improved near-interface characteristics enabled by the formation of the gate stack at a temperature of 100° C.

Physisorbed-precursor-assisted atomic layer deposition of reliable ultrathin dielectric films on inert graphene surfaces for low-power electronics

Among the most fundamental challenges encountered in the successful incorporation of graphene in silicon-based electronics is the conformal growth of ultrathin dielectric films, especially those with thicknesses lower than 5 nm, on chemically inert graphene surfaces. Here, we present physisorbed-precursor-assisted atomic layer deposition (pALD) as an extremely robust method for fabricating such films. Using atomic-scale characterisation, it is confirmed that conformal and intact ultrathin Al2O3 films can be synthesised on graphene by pALD. The mechanism underlying the pALD process is identified through first-principles calculations based on density functional theory. Further, this novel deposition technique is used to fabricate two types of wafer-scale devices. It is found that the incorporation of a 5 nm-thick pALD Al2O3 gate dielectric film improves the performance of metal-oxide-graphene field-effect transistors to a greater extent than does the incorporation of a conventional ALD Al2O3 film. We also employ a 5 nm-thick pALD HfO2 film as a highly scalable dielectric layer with a capacitance equivalent oxide thickness of 1 nm in graphene-based tunnelling field-effect transistors fabricated on a glass wafer and achieve a subthreshold swing of 30 mV/dec. This significant improvement in switching allows for the low-voltage operation of an inverter within 0.5 V of both the drain and the gate voltages, thus paving the way for low-power electronics.

Mesostructured HfxAlyO2 Thin Films as Reliable and Robust Gate Dielectrics with Tunable Dielectric Constants for High-Performance Graphene-Based Transistors.

We introduce a reliable and robust gate dielectric material with tunable dielectric constants based on a mesostructured HfxAlyO2 film. The ultrathin mesostructured HfxAlyO2 film is deposited on graphene via a physisorbed-precursor-assisted atomic layer deposition process and consists of an intermediate state with small crystallized parts in an amorphous matrix. Crystal phase engineering using Al dopant is employed to achieve HfO2 phase transitions, which produce the crystallized part of the mesostructured HfxAlyO2 film. The effects of various Al doping concentrations are examined, and an enhanced dielectric constant of ∼25 is obtained. Further, the leakage current is suppressed (∼10(-8) A/cm(2)) and the dielectric breakdown properties are enhanced (breakdown field: ∼7 MV/cm) by the partially remaining amorphous matrix. We believe that this contribution is theoretically and practically relevant because excellent gate dielectric performance is obtained. In addition, an array of top-gated metal-insulator-graphene field-effect transistors is fabricated on a 6 in. wafer, yielding a capacitance equivalent oxide thickness of less than 1 nm (0.78 nm). This low capacitance equivalent oxide thickness has important implications for the incorporation of graphene into high-performance silicon-based nanoelectronics.

An improvement of HfO2/Ge interface by in situ remote N2 plasma pretreatment for Ge MOS devices

In situ remote N2 plasma pretreatment of Ge substrate before deposition of HfO2 is proved effective to reduce GeOx interlayer at the HfO2/Ge interface, resulting in a smaller capacitance equivalent oxide thickness, lower interface trap density and leakage current density for the metal/HfO2/n-Ge capacitors. However, it has no obvious impact on the metal/HfO2/p-Ge capacitors, showing a much higher interface trap density than that on n-Ge. The high equivalent permittivity of the HfO2 gate stacks (∼24.2) confirmed the removal of GeOx interlayer by N2 plasma pretreatment. In situ remote N2 plasma pretreatment is demonstrated perspective to make metal/HfO2/n-Ge MOSFET with scaling capacitance equivalent oxide thickness.

Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors.

The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain a uniform and pinhole-free ALD HfO2 film with a substantially small CET at a wafer scale. The effects of various surface modifications, such as N-methyl-2-pyrrolidone treatment and introduction of sputtered ZnO and e-beam-evaporated Hf seed layers on monolayer graphene, and the subsequent HfO2 film formation under identical ALD process parameters were systematically evaluated. The nucleation layer provided by the Hf seed layer (which transforms to the HfO2 layer during ALD) resulted in the uniform and conformal deposition of the HfO2 film without damaging the graphene, which is suitable for downscaling the CET. After verifying the feasibility of scaling down the HfO2 thickness to achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors, we fabricated graphene heterojunction tunnelling transistors with a record-low subthreshold swing value of <60 mV/dec on an 8″ glass wafer.

Improving the Electrical Properties of Lanthanum Silicate Films on Ge Metal Oxide Semiconductor Capacitors by Adopting Interfacial Barrier and Capping Layers

The electrical properties of La-silicate films grown by atomic layer deposition (ALD) on Ge substrates with different film configurations, such as various Si concentrations, Al2O3 interfacial passivation layers, and SiO2 capping layers, were examined. La-silicate thin films were deposited using alternating injections of the La[N{Si(CH3)3}2]3 precursor with O3 as the La and O precursors, respectively, at a substrate temperature of 310 °C. The Si concentration in the La-silicate films was further controlled by adding ALD cycles of SiO2. For comparison, La2O3 films were also grown using [La((i)PrCp)3] and O3 as the La precursor and oxygen source, respectively, at the identical substrate temperature. The capacitance-voltage (C-V) hysteresis decreased with an increasing Si concentration in the La-silicate films, although the films showed a slight increase in the capacitance equivalent oxide thickness. The adoption of Al2O3 at the interface as a passivation layer resulted in lower C-V hysteresis and a low leakage current density. The C-V hysteresis voltages of the La-silicate films with Al2O3 passivation and SiO2 capping layers was significantly decreased to ∼0.1 V, whereas the single layer La-silicate film showed a hysteresis voltage as large as ∼1.0 V.

Nanoscale Characterization of TiO2 Films Grown by Atomic Layer Deposition on RuO2 Electrodes

Topography and leakage current maps of TiO2 films grown by atomic layer deposition on RuO2 electrodes using either a TiCl4 or a Ti(O-i-C3H7)4 precursor were characterized at nanoscale by conductive atomic force microscopy (CAFM). For both films, the leakage current flows mainly through elevated grains and not along grain boundaries. The overall CAFM leakage current is larger and more localized for the TiCl4-based films (0.63 nm capacitance equivalent oxide thickness, CET) compared to the Ti(O-i-C3H7)4-based films (0.68 nm CET). Both films have a physical thickness of ∼20 nm. The nanoscale leakage currents are consistent with macroscopic leakage currents from capacitor structures and are correlated with grain characteristics observed by topography maps and transmission electron microscopy as well as with X-ray diffraction.

Properties of HfLaO MOS capacitor deposited on SOI with plasma enhanced atomic layer deposition

Amorphous HfLaO dielectric film was successfully deposited on a silicon-on-insulator (SOI) substrate by plasma enhanced atomic layer deposition with in situ plasma treatment. The HfLaO film retained its insulating characteristics and is thermally stable even after annealing at 800 °C. The film has a dielectric constant of 27.3 and leakage of only 0.03 mA/cm2 at a gate bias of |Vg − Vfb| = 1 V. The capacitance equivalent oxide thickness is 0.7 nm. A new parallel electrode testing structure was applied to measure C–V and J–V characteristics for the SOI samples. This testing method for metal–oxide–semiconductor capacitors has potential uses for measuring other layered substrates.

Influence of interlayer properties on the characteristics of high-k gate stacks

The significance of interface sharpness between interlayers and high-k oxides for the properties of transistor gate-stacks has been investigated. Energy band variation in the oxide is calculated by using literature data for the HfO2/SiO2 interface, assuming two different cases for the interface plane: flat with a gradual depth variation of k-value and rough with an abrupt change of k. We demonstrate that the capacitive properties are similar, whereas tunneling properties considerably differ between the two cases. Furthermore, depth distributions of tunneling effective mass and dielectric constant have a substantial influence on the probability for charge carrier tunneling through the oxide stack and for the determination of capacitance equivalent oxide thickness (CET).

Macroscopic and microscopic electrical characterizations of high-k ZrO2 and ZrO2/Al2O3/ZrO2 metal-insulator-metal structures

In order for sub-10 nm thin films of ZrO2 to have a dielectric constant larger than 30 they need to be crystalline. This is done by either depositing the layer at higher temperatures or by a postdeposition annealing step. Both methods induce high leakage currents in ZrO2 based dielectrics. In order to understand the leakage a thickness series of ultrathin ZrO2 and nanolaminate ZrO2/Al2O3/ZrO2 (ZAZ) films, deposited by atomic layer deposition, was investigated. After deposition these films were subjected to different rapid thermal annealing (RTA) processes. Grazing incidence x-ray diffraction and transmission electron microscopy yield that the crystallization of ZrO2 during deposition is dependent on film thickness and on the presence of an Al2O3 sublayer. Moreover, the incorporation of Al2O3 prevents crystallites from spanning across the entire film during RTA. C-V and I-V spectroscopies show that after a 650 °C RTA in N2 the capacitance equivalent oxide thickness of 10 nm ZAZ films is reduced to 1.0 nm while maintaining low leakage currents of 3.2×10−8 A/cm2 at 1 V. Conductive atomic force microscopy studies yield that currents are not associated with significant morphological features in amorphous layers. However, after crystallization, the currents at crystallite grain boundaries are increased in ZrO2 and ZAZ films.

The Effect of Nitrogen in HfOxNy and ZrOxNy on Dielectric Properties and BTI Characteristics

The effect of nitrogen incorporation on the dielectric properties and bias temperature instability characteristics of HfOxNy and ZrOxNy were investigated. The incorporated nitrogen induces a reduction in the capacitance equivalent oxide thickness value, increases the leakage current, and causes the turn around of Vth shift under the positive bias stress in nMOSFET. In addition, compared to HfOxNy, ZrOxNy shows a significantly lower initial Vth shift under positive gate stress due to the lower number of shallow bulk traps related to oxygen vacancies.

The Effect of Hf/(Hf+Si) Ratios in Hf1-xSixOy Dielectric Film on Physical and Electrical Stabilities

Hf1-xSixOy (HfSiO) gate dielectrics with a wide range of Si composition are grown by an atomic layer deposition (ALD). The Si composition in HfSiO films can be tailored with precision by manipulating the ALD sub-cycle sequence of Hf and Si precursors. Through this method, the effects of Si composition of HfSiO films on the physical and electrical properties are investigated with different thermal budget. Si incorporation into HfO2 delays the crystallization of the films, which improved the leakage current characteristics. However, it also increases capacitance equivalent oxide thickness values due to the increased SiO2 content which has a relatively lower dielectric constant. By optimizing the Si composition, high quality HfSiO gate dielectrics having comparable insulator properties to HfO2 but improved thermal stability were achieved

Investigation of ZrO2 – Gd2O3 Based High-k Materials as Capacitor Dielectrics

Atomic layer deposition (ALD) of nanolaminates and mixtures was investigated for the preparation of a high permittivity dielectric material. Variation in the relative number of ALD cycles for constituent oxides allowed one to obtain films with controlled composition. Pure films possessed monoclinic and higher permittivity cubic or tetragonal phases, whereas the inclusion of resulted in the disappearance of the monoclinic phase. Changes in phase composition were accompanied with increased permittivity of mixtures and laminates with low Gd content. Further increase in the lower permittivity content above 3.4 cat. % resulted in the decreased permittivity of the mixtures. Leakage currents generally decreased with increasing Gd content, whereby laminated structures demonstrated smaller leakage currents than mixed films at a comparable Gd content. Concerning the bottom electrode materials, the best results in terms of permittivity and leakage currents were achieved with Ru, allowing a capacitance equivalent oxide thickness of and a current density of at 1 V. Charge storage values up to were obtained for mixtures and laminates with thickness below 30 nm. In general, at electric fields below 2–3 MV/cm, normal and trap-compensated Poole–Frenkel conduction mechanisms were competing, whereas at higher fields, Fowler–Nordheim and/or trap-assisted tunneling started to dominate.

Atomic Layer Deposition and Characterization of Erbium Oxide-Doped Zirconium Oxide Thin Films

films doped with were grown by atomic layer deposition from tris(2,2,6,6-tetramethyl-3,5-heptanedionato)erbium, bis(methylcyclopentadienyl)methoxymethylzirconium, and ozone as precursors at . The erbium content was 1–5 cation %. The films were uniform in thickness. The films were crystallized already in the as-deposited state. Upon annealing at , they were stabilized in the form of cubic or tetragonal polymorph of . Enhancement in capacitance required intense crystallization that was observed when the film thickness exceeded 4.4 nm. The permittivity of the films could reach 31. The capacitors based on the doped possessed lower capacitance equivalent oxide thickness compared to the nondoped and also comparable leakage current densities.

Electrical and Bias Temperature Instability Characteristics of n-Type Field-Effect Transistors Using HfOxNy Gate Dielectrics

The dielectric properties and n-type metal oxide semiconductor field-effect transistor (nMOSFET) positive bias temperature instability (PBTI) characteristics of in situ nitrogen-incorporated plasma-enhanced atomic layer deposited gate dielectrics were compared with those of the films. Although the physical thickness of the and films were almost identical , the capacitance equivalent oxide thickness of (1.43 nm) was much lower than that of (2.28 nm), suggesting that has a larger dielectric constant. However, showed a higher leakage current than due to a decrease in bandgap. showed a turnaround effect under a positive gate stress bias in nMOSFET. The threshold voltage shifted to the positive direction during the first second due to the trapping of electrons at pre-existing trap sites in Hf-based gate dielectrics. Subsequently, the shifted in the negative direction due to hole trapping, which originated from the generation of electron–hole pairs related to the surface plasmon. showed a higher initial interface trap density but a lower interface trap generation rate during n-type MOS PBTI stress than .

Properties of HfO2 and HfO2: Y films grown by atomic layer deposition in an advanced monocyclopentadienyl-based process

Uniform HfO2 and HfO2:Y (7–8 cat.% Y) thin films were grown from a novel cyclopentadienyl-alkylamido precursor CpHf(NMe2)3, (CpMe)3Y and O3 at 300 °C. HfO2:Y films possessed somewhat higher roughness, and crystallized upon annealing at 500 °C in the form of cubic or tetragonal polymorph, compared to monoclinic HfO2 films. HfO2:Y demonstrated lower capacitance equivalent oxide thickness compared to HfO2, although HfO2films occurred slightly better insulating. Higher capacitance required intense crystallization achieved in the films grown to thicknesses exceeding 6 nm.