Cache Configurations Research Articles

ANALISIS EFISIENSI DAN KEAMANAN KONFIGURASI WEB PROXY DALAM MENGELOLA TRAFIK INTERNET DI LINGKUNGAN PENDIDIKAN

Internet use in educational settings is increasing, but can cause problems such as access to inappropriate content, the spread of malware, and misuse of bandwidth. Web proxies can be a solution for managing internet traffic efficiently and safely. This article analyzes the efficiency and security of web proxy configurations in managing internet traffic in educational environments. The efficiency of web proxy configuration is influenced by the type of web proxy, cache configuration, and bandwidth configuration. The security of a web proxy configuration is affected by authentication, content filtration, and software updates. Proper web proxy configuration can increase the efficiency and security of internet access for users in educational environments.

HBPB, applying reuse distance to improve cache efficiency proactively

Cache memories play a significant role in the performance, area, and energy consumption of modern processors, and this impact is expected to grow as on-die memories become larger. While caches are highly effective for cache-friendly access patterns, they introduce unnecessary delays and energy wastage when they fail to serve the required data. Hence, cache bypassing techniques have been proposed to optimize the latency of cache-unfriendly memory accesses. In this scenario, we discuss HBPB, a history-based preemptive bypassing technique that accelerates cache-unfriendly access through the reduced latency of bypassing the caches. By extensively evaluating different real-world applications and hardware cache configurations, we show that HBPB yields energy reductions of up to 75% and performance improvements of up to 50% compared to a version that does not apply cache bypassing. More importantly, we demonstrate that HBPB does not affect the performance of applications with cache-friendly access patterns.

An analysis of cache configuration’s impacts on the miss rate of big data applications using gem5

This work aims to analyze the impacts of cache configurations on miss rates of big data benchmarks with varying level 1 instruction (L1I) and data (L1D) caches using the gem5 simulator. The cache miss rate of nine big data applications from four benchmark suits is analyzed with different cache configurations, such as increasing the cache size, varying the associativity, and altering the line size. The gem5 provides a versatile platform for conducting detailed experiments. The study sheds light on the relationship between cache and big data workloads, thus offering insights into optimizing cache configurations? effect on miss rates for improved performance.

Self Adaptive Logical Split Cache Techniques for Delayed Aging of NVM LLC

Due to the technological advancements in the last few decades, several applications have emerged that demand more computing power and on-chip and off-chip memories. However, the scaling of memory technologies is not at par with computing throughput of modern day multi-core processors. Conventional memory technologies such as SRAM and DRAM have technological limitations to meet large on-chip memory requirements owing to their low packaging density and high leakage power. In order to meet the ever-increasing demand for memory, researchers came up with alternative solutions, such as emerging non-volatile memory technologies such as STT-RAM, PCM, and ReRAM. However, these memory technologies have limited write endurance and high write energy. This emphasizes the need for a policy that will reduce the writes or distribute the writes uniformly across the memory thereby enhancing its lifetime by delaying the early wear out of memory cells due to frequent writes. We propose two techniques, Enhanced-Virtually Split Cache (E-ViSC) and Protean-Virtually Split Cache (P-ViSC), which dynamically adjust the cache configuration to distribute the writes uniformly across the memory to enhance the lifetime. Experimental studies show that E-ViSC and P-ViSC improve lifetime of NVM L2 caches by upto 2.31× and 1.97× respectively.

CACHE DATA REPLACEMENT POLICY BASED ON RECENTLY USED ACCESS DATA AND EUCLIDEAN DISTANCE

Data access management in web-based applications that use relational databases must be well thought out because the data continues to grow every day. The Relational Database Management System (RDBMS) has a relatively slow access speed because the data is stored on disk. This causes problems with decreased database server performance and slow response times. One strategy to overcome this is to implement caching at the application level. This paper proposed SIMGD framework that models Application Level Caching (ALC) to speed up relational data access in web applications. The ALC strategy maps each controller and model that has access to the database into a node-data in the in-Memory Database (IMDB). Not all node-data can be included in IMDB due to limited capacity. Therefore, the SIMGD framework uses the Euclidean distance calculation method for each node-data with its top access data as a cache replacement policy. Node-data with Euclidean distance closer to their top access data have a high priority to be maintained in the caching server. Simulation results show at the 25KB cache configuration, the SIMGD framework excels in achieving hit ratios compared to the LRU algorithm of 6.46% and 6.01%, respectively.

Latency Minimization for Mobile Edge Computing Networks

The proliferation of data-intensive mobile applications is causing latency to become an issue in mobile edge computing (MEC) systems. In this work, we propose a novel methodology that optimizes communication, computation, and caching configurations in MEC to minimize the mean latency experienced by mobile devices. Transmission and computation processes are modeled using M/G/1 queues to account for service rates and warm-up times. Our caching scheme includes time variables for each file at each edge server in determining when to discard files from storage. We theoretically analyze the latency experienced by mobile devices due to communication, computation, and caching, showing how MEC system latency depends on the offloading decisions of mobile devices, bandwidth and CPU resources, and expiration times of files in the storage of edge servers. Our method for solving the latency minimization problem consists of two main components: iNner cOnVex Approximation (NOVA) to deal with non-convexity in the optimization, and an online algorithm for preventing cache storage violations as new tasks arrive and are serviced by the MEC system. Simulation results show that our algorithm outperforms several baselines in minimizing latency, and verify the benefit of including different resource allocation variables in our optimization.

Cocktail Edge Caching: Ride Dynamic Trends of Content Popularity With Ensemble Learning

Edge caching will play a critical role in facilitating the emerging content-rich applications. However, it faces many new challenges, in particular, the highly dynamic content popularity and the heterogeneous caching configurations. In this paper, we propose Cocktail Edge Caching, that tackles the dynamic popularity and heterogeneity through ensemble learning. Instead of trying to find a single dominating caching policy for all the caching scenarios, we employ an ensemble of constituent caching policies and adaptively select the best-performing policy to control the cache. Towards this goal, we first show through formal analysis and experiments that different variations of the LFU and LRU policies have complementary performance in different caching scenarios. We further develop a novel caching algorithm that enhances LFU/LRU with deep recurrent neural network (LSTM) based time-series analysis. Finally, we develop a deep reinforcement learning agent that adaptively combines base caching policies according to their virtual hit ratios on parallel virtual caches. Through extensive experiments driven by real content requests from two large video streaming platforms, we demonstrate that CEC not only consistently outperforms all single policies, but also improves the robustness of them. CEC can be well generalized to different caching scenarios with low computation overheads for deployment.

Hierarchical cache configuration based on hybrid SOT- and STT-MRAM

With the rapid growth of big data information and the continuous iteration progress of CPU architecture, the implementation of a new memory-based cache architecture is urgent and challenging. In the paper, a CPU cache architecture system based on MRAM is built. Firstly, the performance of SRAM, STT-MRAM and SOT-MRAM as caches from 8 kb to 32 Mb is evaluated. Secondly, by summarizing the performance of SRAM and MRAM in different cache levels, a new quad-core CPU cache architecture design scheme with SOT-MRAM as the first level of cache and STT-MRAM as the second level of cache is determined. Thirdly, the built cache system is simulated. A non-inclusive strategy is proposed to replace the inclusive strategy in order to solve the problem of high dynamic energy of STT-MRAM at the second level. The idea of having a quad-core CPU dynamically share the second-level cache is proposed in the paper. Finally, the caching system in the paper is compared with the other previous works, showing up to 60.78% energy consumption advantage and 33.22% leakage power advantage. The proposed MRAM-based CPU cache system and the corresponding cache strategy have potential application with the benefits of low power and less area.

Evaluation on the Impact of Cache Parameter Selection in Access-Driven Cache Attacks

Cache attacks exploit the hardware vulnerabilities inherent to modern processors and pose a new threat to Internet of Things (IoT) devices. Intuitively, different cache parameter configurations directly impact the attack effectiveness, but the current research on this issue is not systematic or comprehensive enough. This paper’s primary focus is to evaluate how different cache parameter configurations affect access-driven attacks. We build a flexible and configurable simulation verification environment based on the Chipyard framework. To reduce the interference of other factors, we established a baseline for each category of parameter evaluation. We propose a novel evaluation model, called Key Score Scissors Differential (KSSD), for evaluating common private and shared cache parameters under the local and cross-core attack models, respectively; among these are private cache replacement policy, private cache capacity, cache line size, private cache associativity, shared cache capacity, and shared cache associativity. Ours is the first evaluation of the shared cache under a cross-core attack model. As a result of the evaluation, the quantitative metrics can provide a reliable indication of information leakage level under the current cache configuration, which is helpful for attackers, defenders, and evaluators. Furthermore, we provide detailed explanations and discussions of inconsistent findings by comparing our results with the existing literature.

An End-to-End Automatic Cache Replacement Policy Using Deep Reinforcement Learning

In the past few decades, much research has been conducted on the design of cache replacement policies. Prior work frequently relies on manually-engineered heuristics to capture the most common cache access patterns, or predict the reuse distance and try to identify the blocks that are either cache-friendly or cache-averse. Researchers are now applying recent advances in machine learning to guide cache replacement policy, augmenting or replacing traditional heuristics and data structures. However, most existing approaches depend on the certain environment which restricted their application, e.g, most of the approaches only consider the on-chip cache consisting of program counters (PCs). Moreover, those approaches with attractive hit rates are usually unable to deal with modern irregular workloads, due to the limited feature used. In contrast, we propose a pervasive cache replacement framework to automatically learn the relationship between the probability distribution of different replacement policies and workload distribution by using deep reinforcement learning. We train an end-to-end cache replacement policy only on the past requested address through two simple and stable cache replacement policies. Furthermore, the overall framework can be easily plugged into any scenario that requires cache. Our simulation results on 8 production storage traces run against 3 different cache configurations confirm that the proposed cache replacement policy is effective and outperforms several state-of-the-art approaches.

Network Performance of Proxy-Enabled Server Using Three Configurations

Background: This study aimed to test the mean network performance of the proxy server from the Out-Of-The-Box (OOTB), caching, filtering, and bandwidth allocation configurations when categorized according to the time of access and type of websites. More so, determine significant differences in the network performance of the proxy server with the OOTB and compared it with caching, blocking, and bandwidth allocation configuration when categorized according to the time of access and type of websites. Methods: Experimental design was employed to determine the difference in the network performance of proxy servers using three configurations namely, caching, filtering, and bandwidth allocation as compared to the network performance of proxyserver with the OOTB configuration. These three configurations were made as independent variables that determined the network performance of a proxyenabled server. The researchers used the Squid Proxy version 3.4. The data were obtained by setting up a computer system running Ubuntu Linux version 19.10. Four sets of experiments were conducted to test the performance of the OOTB, caching, filtering and bandwidth allocation configurations simultaneously. The time of access was defined as A.M. session and P.M. session while the type of websites was defined as static webpages and dynamic webpages. The mean and t-Test were the statistical tools used in the study where t-Test was set at 0.05 alpha level. Findings: It was found out that the caching configuration, in both time of access and type of websites, was the most efficient among the three configurations. The proxy-enabled server with blocking configuration was found to have the least performance efficiency for both times of access and types of websites among the three configurations. Novelty : With the results of this study, it is highly recommended to network administrators to employ caching configuration on proxy servers to improve the performance efficiency of computer networks. Keywords: ProxyServer; OutOfTheBox; Caching; Filtering; Bandwidth Allocation

A dynamic ICN and IoT based caching method supporting high‐tech transformation

In the Information Center Network (ICN) and Internet of Things (IoT) integrated environment, the existing cache research mainly realizes the cache configuration of high‐tech content in a single dimension such as content popularity or freshness. In view of the above conditions, this paper first analyzes the characteristics of high‐tech transformation, and combines the data characteristics of the Internet of things, divides the data into periodic data and event triggered data. Then, considering these two data characteristics of the Internet of things, an ICN‐IoT cache scheme with different cache decisions is proposed to accelerate the transformation of high‐tech. Simulation results show that the scheme can improve the difference rate of high‐tech content, increase the diversity of cache content, improve the cache hit rate, and then meet the needs of different high‐tech transformation.

A Configurable and Real-Time Multi-Frequency 3D Image Signal Processor for Indirect Time-of-Flight Sensors

3D time-of-flight (ToF) cameras have recently attracted widespread attention because of their potential in wide applications. However, the lack of versatile 3D image signal processor (ISP) is still an obstacle that hinders their popularity. The main challenges lie in the management of high-throughput raw data and the complexity of 3D image processing in hardware. To address these challenges, this paper presents a top-down 3D ISP with high real-time performance and high energy efficiency for indirect ToF (IToF) imaging. First, we propose configurable cache strategies to improve the efficiency of non-streaming memory accesses and support different IToF sensors. Then, to resolve the phase ambiguity problem commonly existing in IToF sensors, we develop a hardware-optimized cascaded multi-frequency fusion method, which not only supports up to six modulation frequencies but also facilitates the pixel-wise detection of multipath interference. Moreover, we propose a scalable calculation engine for depth calculation and calibration, 3D image enhancement, and post-processing. The pipeline is prototyped on a Xilinx ZCU102 FPGA board. Results show that the 3D ISP has negligible precision loss and low latency, achieving <inline-formula> <tex-math notation="LaTeX">$53.35\times $ </tex-math></inline-formula> energy efficiency improvement compared with the implementation on Intel CPU and <inline-formula> <tex-math notation="LaTeX">$55.45\times $ </tex-math></inline-formula> improvement over the ARM CPU implementation. When running at 75 MHz, the 3D ISP can support <inline-formula> <tex-math notation="LaTeX">$1280\times 960$ </tex-math></inline-formula> depth, intensity, and point cloud output at a frame rate of 30 f/s.

High performance and energy efficient inference for deep learning on multicore ARM processors using general optimization techniques and BLIS

We evolve PyDTNN, a framework for distributed parallel training of Deep Neural Networks (DNNs), into an efficient inference tool for convolutional neural networks. Our optimization process on multicore ARM processors involves several high-level transformations of the original framework, such as the development and integration of Cython routines to exploit thread-level parallelism; the design and development of micro-kernels for the matrix multiplication, vectorized with ARM’s NEON intrinsics, that can accommodate layer fusion; and the appropriate selection of several cache configuration parameters tailored to the memory hierarchy of the target ARM processors.Our experiments evaluate both inference throughput (measured in processed images/s) and inference latency (i.e., time-to-response) as well as energy consumption per image when varying the level of thread parallelism and the processor power modes. The experiments with the new inference engine are reported for the ResNet50 v1.5 model on the ImageNet dataset from the MLPerf suite using the ARM v8.2 cores in the NVIDIA Jetson AGX Xavier board. These results show superior performance compared with the well-spread TFLite from Google and slightly inferior results when compared with ArmNN, the native library from ARM for DNN inference.

The Impact of Cache and Dynamic Memory Management in Static Dataflow Applications

Dataflow is a parallel and generic model of computation that is agnostic of the underlying multi/many-core architecture executing it. State-of-the-art frameworks allow fast development of dataflow applications providing memory, communicating, and computing optimizations by design time exploration. However, the frameworks usually do not consider cache memory behavior when generating code. A generally accepted idea is that bigger and multi-level caches improve the performance of applications. This work evaluates such a hypothesis in a broad experiment campaign adopting different multi-core configurations related to the number of cores and cache parameters (size, sharing, controllers). The results show that bigger is not always better, and the foreseen future of more cores and bigger caches do not guarantee software-free better performance for dataflow applications. Additionally, this work investigates the adoption of two memory management strategies for dataflow applications: Copy-on-Write (CoW) and Non-Temporal Memory transfers (NTM). Experimental results addressing state-of-the-art applications show that NTM and CoW can contribute to reduce the execution time to -5.3% and \(-15.8\%\), respectively. CoW, specifically, shows improvements up to -21.8% in energy consumption with -16.8% of average among 22 different cache configurations.

Research on Vehicle-to-Road Collaboration and End-to-End Collaboration for Multimedia Services in the Internet of Vehicles

With the development of mature communication network technologies such as 5G, edge computing and slicing, business applications in areas such as telematics and intelligent transportation need the support of vehicle-road collaboration technologies. Due to the mobility of vehicles and the heterogeneity of communication interfaces, there are many challenges for data transmission and the processing of telematics. Therefore, network resources, roadside unit devices and sunken edge nodes need to work together to guarantee real-time network communication. Thus, they can jointly help improve the quality of network services and user experience and show the level of vehicle-road collaboration in terms of safety, efficiency and service. In view of future 5G network-related technologies and C-V2X development trends, this paper provides a comprehensive technical solution framework for telematics based on end-edge collaboration, and combines network resource deployment optimization and edge caching technologies for video transmission tasks in telematics application scenarios. By adding both a 5G base roadside unit (RSU) station and an UAV mobile base station, network resources are better allocated for scalable coded video, and a relatively better edge caching strategy is obtained based on user mobility analysis. Aiming to improve the network system performance, the vehicle side, roadside and edge side are jointly considered to improve the utilization efficiency of limited network resources. In this paper, we hope to provide a practical and effective service architecture for telematics video application scenarios through a convergence scheme of network resource allocation and edge caching configuration.

Modeling cache performance for embedded systems

This paper presents a cache performance model for embedded systems. The need for efficient cache design in embedded systems has led to the exploration of various methods of design for optimal cache configurations for embedded processor. Better users’ experiences are realized by improving performance parameters of embedded systems. This work presents a cache hit rate estimation model for embedded systems that can be used to explore optimal cache configurations using Bourneli’s binomial cumulative probability based on application of reuse distance profiles. The model presented was evaluated using three mibench benchmarks which are bitcount, basicmath and FFT for 4kb, 8kb, 16kb, 32kb and 64kb sizes of cache under 2-way, 4-ways, 8-ways and 16-ways set associative configurations, all using least recently-used (LRU) replacement policy. The results were compared with the results obtained using sim-cheetah from simplescalar simulators suite. The mean errors for bitcount, basicmath, and FFT benchmarks are 0.0263%, 2.4476%, and 1.9000% respectively. Therefore, the mean error for the three benchmarks is equal to 1.4579%. The margin of errors in the results was below 5% and within the acceptable limits showing that the model can be used to estimate hit rates of cache and to explore cache design options.

Enhancing Security in Key Management Using Hybrid Cache Supported One Way Hash Chain Technique

Background: Collusion resistance is preserving the value generated at individual nodes secret so that if any nodes share the information together or collude with each other, the secret values cannot be revealed.It is really a challenging task to securely resist the collusion of cloud server and users Collusion resistance also involves growing the number of people. Objective: Users can achieve an effective and economical approach for data sharing among group members in the cloud with the characters of low maintenance and little management cost. Method: Hybrid Cache supported One way hash chain Technique. Result: To test with the sparse caching HHCS and one-way hash chain model and the various sparse caching configurations are fully implemented by this work. Multiple situations and various scenarios are considered in the experiments and tests for the estimation of HHCS’ performance. The results which are measured in terms of storage units needed for the completion of one internet session and in terms of efficiency (which is the number of hash operations done in one session) are compared and then contrasted. Conclusion: Security improvement is proposed in this paper in group key management method, in order to solve the issue of collusion attack between whole members of the group for a secure group communication. It is shown that using lightweight is easy for the implementation of sparse caching method which can greatly improve the cryptographic one-way hash chain method’s performance which is used widely, for securing the transmission of data in cloud by using two levels of security scheme. A memory-times computation complexity metric has been introduced to help choose the best size of cache depending on storage requirements of the cloud application. For demonstrating various connection behaviors, various cache spacing methods have been evaluated. This paper presented and evaluated the potential of hybrid solution in which one-way hash chains which are divided are provided with caching capacities in order to store the values of session key and retrieve them when needed for authenticating a user session. Lower computational overhead is achieved by us as measured by the count of hash operations and computation time needed to give protection.

IOb-Cache: A High-Performance Configurable Open-Source Cache

Open-source processors are increasingly being adopted by the industry, which requires all sorts of open-source implementations of peripherals and other system-on-chip modules. Despite the recent advent of open-source hardware, the available open-source caches have low configurability, limited lack of support for single-cycle pipelined memory accesses, and use non-standard hardware interfaces. In this paper, the IObundle cache (IOb-Cache), a high-performance configurable open-source cache is proposed, developed and deployed. The cache has front-end and back-end modules for fast integration with processors and memory controllers. The front-end module supports the native interface, and the back-end module supports the native interface and the standard Advanced eXtensible Interface (AXI). The cache is highly configurable in structure and access policies. The back-end can be configured to read bursts of multiple words per transfer to take advantage of the available memory bandwidth. To the best of our knowledge, IOb-Cache is currently the only configurable cache that supports pipelined Central Processing Unit (CPU) interfaces and AXI memory bus interface. Additionally, it has a write-through buffer and an independent controller for fast, most of the time 1-cycle writing together with 1-cycle reading, while previous works only support 1-cycle reading. This allows the best clocks-per-Instruction (CPI) to be close to one (1.055). IOb-Cache is integrated into IOb System-on-Chip (IOb-SoC) Github repository, which has 29 stars and is already being used in 50 projects (forks).

Design and Implementation of Configurable Cache Coherence Protocol for Multi-Core Processor

Design and Implementation of Configurable Cache Coherence Protocol for Multi-Core Processor