Cache-based Side-channel Attacks Research Articles

On Preventing and Mitigating Cache Based Side-Channel Attacks on AES System in Virtualized Environments

Cloud computing aims to cut costs through a reduction in spending on equipment, infrastructure, and software by applying the multi-tenancy feature. Despite all the benefits of multi-tenancy, it is still a source of risk in cloud computing. Cloud adoption may be hampered by security concerns if suitable cloud-based security solutions are not available. Moreover, virtualization that enables multi-tenancy, considered one of the main components of a cloud, introduces major security risks and does not offer appropriate isolation between different instances running on the same physical machine. In this paper, we present a preliminary idea that may support the development of new countermeasures for a particular type of threat, namely cache-based side-channel attacks that target cache memories in virtualized environments. Attackers specifically target virtual machines in this type of attack to create many side channels and gather sensitive data. Additionally, this research offers preliminary concepts to aid in developing of solutions or defenses that enable us to identify unusual activity that could point to attacks associated with multi-tenancy, as well as security measures that preserve the benefits of multi-tenancy while lowering security concerns.

Toward an Optimal Countermeasure for Cache Side-Channel Attacks

In the last 15 years, we have witnessed a never ending arm’s race between the attacker and the defender with respect to cache-based side-channel attacks. We have seen a slew of attacks, countermeasures (CMs), counterattacks, counter-countermeasures and so on. We analyze the evolution of this area, propose three necessary conditions for designing a successful CM, and then analyze timing and address-based CMs for popular algorithms such as AES and PRESENT. We show that an optimal yet trivial solution for timing-based CMs is possible. Furthermore, address-based CMs are inferior to timing-based CMs, and they can be broken in O(nlog(log(n))) time.

Fight Hardware with Hardware: Systemwide Detection and Mitigation of Side-channel Attacks Using Performance Counters

We present a kernel-level infrastructure that allows systemwide detection of malicious applications attempting to exploit cache-based side-channel attacks to break the process confinement enforced by standard operating systems. This infrastructure relies on hardware performance counters to collect information at runtime from all applications running on the machine. High-level detection metrics are derived from these measurements to maximize the likelihood of promptly detecting a malicious application. Our experimental assessment shows that we can catch a large family of side-channel attacks with a significantly reduced overhead. We also discuss countermeasures that can be enacted once a process is suspected of carrying out a side-channel attack to increase the overall tradeoff between the system’s security level and the delivered performance under non-suspected process executions.

Cache-Based Side-Channel Attack Mitigation for Many-Core Distributed Systems via Dynamic Task Migration

Side-channel attacks (SCA) are a serious threat to cryptographic systems due to mostly unavoidable information leakage. Cache-based SCAs take advantage of cache inherent timing properties on shared memory systems to extract security-critical information. In this paper, we present a novel approach to mitigate cache-based SCAs on distributed many-core systems, based on a resource management technique. Our solution leverages dynamic task migration as a mechanism to ensure a secure execution scenario for security-critical applications. Additionally, we propose a resource-management-based mechanism to ensure a secure execution when migration is not possible due to a lack of available resources. We evaluate our solution in terms of gained security and performance impact using the Sniper simulator for different configurations. Results show that our technique effectively develops resilience against SCAs, while causing a low performance slowdown (1.6% on average, 9% worst case). For all tested benchmarks, our worst-case performance slowdown is 20% less than a state-of-the-art countermeasure. Moreover, our solution utilizes less than 1 ms of system run-time overhead for a 64 core platform with 100% utilization.

Transient Execution and Side Channel Analysis: a Vulnerability or a Science Experiment?

In the world of computer security, attackers are constantly looking for new exploits to gain data from or control over a computer system. One category of exploit that can prove quite effective at accessing privileged data is side channel exploits. These exploits attempt to take advantage of vulnerabilities that are inherent in the design of a system rather than vulnerabilities in the code that has been written for and is running on said system. In other words, they exploit side effects of computation. Examples of this include measuring the power consumption of a system’s processor over time and analysing that power usage to leak system secrets or reading secrets from a system by analysing the electromagnetic radiation the system leaks as it processes data. Another type of side channel attack is a cache-based side channel attack, which exploits the timings of cache and memory accesses to determine data from the target system. We discuss some of the more common types of side channel attacks used to interpret data values from the microarchitectural changes created by transient executions. In particular, we will focus on attacks that are capable of recovering data that is processed through transient execution in some way and then wrongly accessed using a side channel, such as the Spectre and Meltdown classes of attack. We also discuss other attacks of a similar type and survey some popular mitigations for these attacks. We provide a survey of all available Spectre proof-of-concept repositories on GitHub, evaluating whether they work on different platforms. Finally, we review our experiences with these types of attacks on modern systems and comment on the attacks’ practicality, reliability, and portability. We conclude that these types of attacks are interesting, but there are some practicality and reliability concerns that make other attacks easier much of the time.

Thwarting Cache Side Channel Attacks with Encryption Address-Based Set Balance Cache

The deterministic memory-to-cache mapping used by cache side channel attack causes the leakage of sensitive information such as secret keys, which seriously threatens user security and highlights the need to defend against this kind of attack. Recent table-based secure cache design requires more space to store the entry while a purely encryption-based design needs complex encryption units to ensure robustness. What is more, the newer attack algorithm enabling faster eviction set discovery may still break such defenses. Even though increasing the association of cache can be a potential solution, it introduces too much redundancy cache access and storage overhead. In this paper, we eliminate this problem. We present Encryption address-based Set Balance Cache (ESBC), a novel cache design to mitigate cache-based side channel attack. ESBC encrypts an address into two-level sets and displaces the data from a primary set into the secondary set when the primary set is full. The two-level mapping structure increases the complexity for attackers to build eviction sets, which is a vital step for the conflict-based attack. Furthermore, we adopt two different optimized variants from a temporal perspective, ESBC with remapping (ESBCR), which serves dynamic-remapping, and spatial perspective, ESBC with multi-mapping (ESBCM), which performs multi-mapping to improve the robustness. Our security analysis reveals that these designs can confuse the exploitation of conflicting addresses. Simulation-based evaluation on SPEC2017 shows 0.24% instruction per cycle (IPC) degradation for ESBCR with 1% remap rate. While the reduction of ESBCM that has five potential secondary sets is 0.69%. What is exciting is that both miss per kilo instructions (MPKI) and miss rates are even reduced because of the efficient cache usage. The storage overhead of these two variants is only 0.87%. By comparing the two schemes, we can observe that though ESBCR brings less performance overhead, the ESBCM has better scalability.

Partitioned Real-Time Scheduling for Preventing Information Leakage

Recent real-time systems have been gradually connected externally through the Internet. As each subsystem constituting a system has been developed from different vendors, the number of cases of security vulnerabilities in communication between subsystems has increased. In particular, real-time systems are vulnerable to timing inference attacks, such as cache-based side-channel attacks. Among the various methods for handling security problems of these systems, the flush task (FT) method is a simple and effective method to reduce the probability of information leakage by conditionally initializing the state of resources shared by tasks before a given scheduling. However, existing FT methods are for global scheduling only, and techniques for partitioned scheduling have not yet been studied. In this paper, we propose an FT-aware bin-packing (FT-bin-packing) algorithm that effectively allocates real-time tasks to identical multiprocessors to reduce the number of FTs invoked during the schedule of tasks in each processor. Based on the experimental results, we analyze the properties and performance of the FT-bin-packing algorithm. These results indicate that it can improve the performance of existing heuristic algorithms by up to 96.8% depending on the experimental setting.

SpecSafe: detecting cache side channels in a speculative world

The high-profile Spectre attack and its variants have revealed that speculative execution may leave secret-dependent footprints in the cache, allowing an attacker to learn confidential data. However, existing static side-channel detectors either ignore speculative execution, leading to false negatives, or lack a precise cache model, leading to false positives. In this paper, somewhat surprisingly, we show that it is challenging to develop a speculation-aware static analysis with precise cache models: a combination of existing works does not necessarily catch all cache side channels. Motivated by this observation, we present a new semantic definition of security against cache-based side-channel attacks, called Speculative-Aware noninterference (SANI), which is applicable to a variety of attacks and cache models. We also develop SpecSafe to detect the violations of SANI. Unlike other speculation-aware symbolic executors, SpecSafe employs a novel program transformation so that SANI can be soundly checked by speculation-unaware side-channel detectors. SpecSafe is shown to be both scalable and accurate on a set of moderately sized benchmarks, including commonly used cryptography libraries.

VM placement and cache based side channel attack at computational level in cloud computing : A Survey

There are different issues that need to focus in respect of security and privacy. One of the most security issue at computational level implementation of secure virtualization is cloud computing. In this, we explain virtualization security and their existing defense system at computational level. In computational level need to increase security of cloud and categorized the virtual machine level security challenges that are faced by cloud users at computational level in cloud computing. Day by day cloud attribute are introducing new challenges in cloud environment. In this paper, we focus on cloud security at computational level. In the day scenario to secure a cloud data on shared environment is the important task for IT industries. In virtual environment need to focus on secure VM placement on the host machine that is running on cloud. This paper demonstrates lack of VM placement and side channel attack (SCA). Analysis of different type of scheme is done and comparative study of game theory based, graph theory based and bin packing VM placement scheme. Also we discussed virtualization in cloud computing and their security aspects and comparative study of different type side channel attack (SCA).

Survey of CPU Cache-Based Side-Channel Attacks: Systematic Analysis, Security Models, and Countermeasures

Privacy protection is an essential part of information security. The use of shared resources demands more privacy and security protection, especially in cloud computing environments. Side-channel attacks based on CPU cache utilize shared CPU caches within the same physical device to compromise the system’s privacy (encryption keys, program status, etc.). Information is leaked through channels that are not intended to transmit information, jeopardizing system security. These attacks have the characteristics of both high concealment and high risk. Despite the improvement in architecture, which makes it more difficult to launch system intrusion and privacy leakage through traditional methods, side-channel attacks ignore those defenses because of the shared hardware. Difficult to be detected, they are much more dangerous in modern computer systems. Although some researchers focus on the survey of side-channel attacks, their study is limited to cryptographic modules such as Elliptic Curve Cryptosystems. All the discussions are based on real-world applications (e.g., Curve25519), and there is no systematic analysis for the related attack and security model. Firstly, this paper compares different types of cache-based side-channel attacks. Based on the comparison, a security model is proposed. The model describes the attacks from four key aspects, namely, vulnerability, cache type, pattern, and range. Through reviewing the corresponding defense methods, it reveals from which perspective defense strategies are effective for side-channel attacks. Finally, the challenges and research trends of CPU cache-based side-channel attacks in both attacking and defending are explored. The systematic analysis of CPU cache-based side-channel attacks highlights the fact that these attacks are more dangerous than expected. We believe our survey would draw developers’ attention to side-channel attacks and help to reduce the attack surface in the future.

An optimistic technique to detect Cache based Side Channel attacks in Cloud

Data security is the most critical field in Cloud Computing. The Critical data can leak through unpredictable side channels, posing very risky threats to information security. The Cache-based Side Channel Attacks (CSCAs) is one of the most challenging attacks. Different secure cache architectures have been proposed to defend against these attacks. But these solutions are not reliable to detect and prevent those attacks. Detection of CSCAs is a very important research-related problem. In this paper we demonstrated the detection of CSCAs. We measured the vCPU cycle, virtual memory utilization and cache miss rate to detect the attackers. We illustrated Prime + Probe attack, Flush + Flush attack, and Flush + Reload attack on the AES cryptosystem. Our detection technique is compared with the existing detection solution to demonstrate the accuracy. Our proposed work is achieved 92.5% accuracy to detect the CSC attacks. With the help of our proposed system the Cloud Service Providers(CSPs) can identify the attackers of VMs and host machines to safe guard victim users from the CSCA.

Survey on Cache-Based Side-Channel Attacks in Cloud Computing

Survey on Cache-Based Side-Channel Attacks in Cloud Computing

Survey of Access-Driven Cache-Based Side Channel Attack

Survey of Access-Driven Cache-Based Side Channel Attack

Meet the Sherlock Holmes’ of Side Channel Leakage: A Survey of Cache SCA Detection Techniques

Cache Side Channel Attacks (SCAs) have gained a lot of attention in the recent past. Since, these attacks exploit the caching hardware vulnerabilities, they are fast and dangerous. Detection of cache side channel attacks is an important step towards mitigating against such hostile entities. Researchers have already proposed different techniques to detect cache side channel attacks. This paper provides a detailed survey of literature related to the state-of-the-art detection techniques for cache based side channel attacks. We identify a set of important characteristics that can be used to characterize a CSCA (cache side channel attack) detection technique. We use the identified features to compare and contrast the most important detection techniques and provide the important observations. We also identify some of the challenges that the research community will have to resolve in future to improve the efficiency of cache side channel detection techniques. To the best of our knowledge, this is the first work to do such a study. We believe that this paper will prove useful to researchers in the area of systems security.

FLUSH + PREFETCH: A countermeasure against access-driven cache-based side-channel attacks

Cache-based side-channel attacks (SCAs) are becoming a security threat to the emerging computing platforms. To mitigate these attacks, numerous countermeasures have been proposed. However, these countermeasures require either radical hardware modification or they are incompatible with the performance features like super-page and data de-duplication. This paper presents a countermeasure, called Flush+Prefetch, which obfuscates the memory access behavior of a secure application using independent threads that randomly access the memory belonging to secure application. Unlike existing state-of-the-art countermeasures, Flush+Prefetch works with commodity hardware and it is compatible with existing performance features. As a proof-of-concept, we have studied the effectiveness of Flush+Prefetch by defending the secret key of RSA cryptosystem against a high-resolution cache side-channel attack called Flush+Reload. We have evaluated the confidentiality of RSA decryption process on an Intel Xeon E5-2643 processor by generating 100, 000 requests to a web-server sequentially while considering the effect on performance as well. Our experimental results show that the confidentiality of memory accesses by RSA is preserved under Flush+Prefetch countermeasure. Our results show that the performance, in terms of average execution time, is improved by 10.2% for best design case as compared to the system under attack.

Detecting Cache-Based Side Channel Attacks in IaaS using Enhanced Algorithm

The Connectivity of the information among people throughout the world is made possible through computers and smart devices connected over the internet. The economic related transactions also happen over the network which needs a secured transaction medium. Therefore, lots of intrusion detection and prevention systems are implemented in order to reduce the impact of the attack. But every year the impact of attack over the shared VMs is being dramatically increased. The economic transactions occur with the help of web applications and they are divided into browser-side and server-side components. One of the major services provided by the cloud environment is Infrastructure-asa-Service in which the virtual machines are used to provide the shared services to the multiple users. Though the VMs are secured by implementing the various security algorithms, one of the attacks, Side-channel attack, uses the leaked information acquired from the implementation of hardware component. Cache-based side channel attack is the serious attack, which tries to steal the sensitive information like credit card details, password, medical related details, etc., by establishing various algorithms like PRIME+PROBE, FLUSH+RELOAD, FLUSH+FLUSH, etc.,. The VM does speculative execution for improving the CPU performance, thus resulting in a scenario which allows the user to access the sensitive data on the cache line. So in this paper the environment is set up with 5 various scenarios with the combinations consisting of attack, no-attack, Full load, Average load and no-load. The Hardware Performance Counters (HPC) is used along with Intel CMT to monitor and distinguish the attacker VM, thus increasing the detection accuracy and reducing the system overhead.

Context-Sensitive Decoding: On-Demand Microcode Customization for Security and Energy Management

Modern instruction set decoders feature translation of native instructions into internal micro-ops to simplify the CPU design and improve instruction-level parallelism. However, this translation is static in most known instances. This paper proposes context-sensitive decoding, a technique that enables customization of the micro-op translation based on the current execution context and/or preset hardware events. Further, it can transition between different translation modes rapidly. While there are many potential applications, this paper demonstrates its effectiveness with two use cases: 1) as a novel security defense to thwart instruction/data cache-based side-channel attacks; and 2) as a power management technique that performs selective devectorization to enable efficient unit-level power gating.

CacheSCDefender: VMM-based Comprehensive Framework against Cache-based Side-channel Attacks

CacheSCDefender: VMM-based Comprehensive Framework against Cache-based Side-channel Attacks

A Way to Improve the Key Recovery Accuracy Based on Dynamic Programming

Key-recovery technology is often used by an adversary to attempt to recover the cryptographic key of an encryption scheme. The most obvious key-recovery attack is the exhaustive key-search attack. But modern ciphers often have a key space of size 2128 or greater, making such attacks infeasible with current technology. Cache-based side channel attack is another way to get the cryptographic key of an encryption scheme, but there are random noises in side channel attack. In order to reduce random errors, it is advisable to repeat the key recovery process many times. This paper is focused on the way to improve the key recovery accuracy by dealing with the key sequences obtained from the repeated Cache-based side channel attacks. To get the real key, private key bits from side channel attack are collected firstly. And then the key sequences are aligned using sequence alignment algorithms based on dynamic programming. The provided method of key recovery is universal, which is not limited to any cryptographic algorithm. The experiment shows that the proposed method has a good performance and a high availability when the error rate of the collected key bit is within a reasonable range.

Adaptive multilevel fuzzy-based authentication framework to mitigate Cache side channel attack in cloud computing

Cloud computing supports multitenancy to satisfy the users’ demands for accessing resources and simultaneously it increases revenue for cloud providers. Cloud providers adapt multitenancy by virtualizing the resources, like CPU, network interfaces, peripherals, hard drives and memory using hypervisor to fulfill the demand. In a virtualized environment, many virtual machines (VMs) can run on the same core with the help of the hypervisor by sharing the resources. The VMs running on the same core are the target for the malicious or abnormal attacks like side channel attacks. Among various side channel attacks in cloud computing, cache-based side channel attack is one that leaks private information of the users based on the shared resources. Here, as the shared resource is the cache, a process can utilize the cache usage of another by cache contention. Cache sharing provides a way for the attackers to gain considerable information so that the key used for encryption can be inferred. Discovering this side channel attack is a challenging task. This requires identification of a feature that influences the attack. Even though there are various techniques available in the literature to mitigate such attacks, an effective solution to reduce the cache-based side channel attack is still an issue. Therefore, a novel fuzzy rule-based mechanism is integrated to detect the cache side channel attackers by monitoring the cache data access (CDA). The factor that determines the attack is CDA in a log file created by the framework during authorization. The proposed framework also utilizes certain security properties including ECC and hashing for the privacy preservation and the decision is made with the aid of a fuzzy logic system.