C-axis Aligned Crystalline Oxide Semiconductor Research Articles

Demonstration of scaling and monolithic stacking for higher integration of integrated circuit using c-axis aligned crystalline oxide semiconductor FET

C-axis-aligned crystalline oxide semiconductor (CAAC-OS) FETs exhibit extremely low off-state leakage current and thus are suitable for low-power devices. Furthermore, CAAC-OS FETs can be integrated in the back end of line process and are promising as memory devices. For higher integration using the CAAC-OS FETs, we examined scaling and monolithic stacking. In addition, we present a 3D dynamic random access memory prototype, which is formed using three-layer monolithically stacked CAAC-OS FETs on a Si-CMOS and exhibits long-term data retention owing to the ultralow off-leakage current. These techniques will contribute to higher speed and integration of memory devices.

5291 ppi OLED Display with C-Axis Aligned Crystalline Oxide Semiconductor

5291 ppi OLED Display with C-Axis Aligned Crystalline Oxide Semiconductor

5291 ppi OLED Display with C-Axis Aligned Crystalline Oxide Semiconductor

5291 ppi OLED Display with C-Axis Aligned Crystalline Oxide Semiconductor

76‐2: Field‐Effect Transistor with CAAC/CAC‐OS Double‐Layer Structure for Diversion of Gen 8‐10.5 Amorphous Silicon Production Lines

Using an active layer in which a c‐axis‐aligned crystalline oxide semiconductor (CAAC‐OS) is stacked on a cloud‐aligned composite OS (CAC‐OS), we have succeeded in fabricating a channel‐etched field‐effect transistor (CE‐FET) with a high on‐state current and favorable reliability. The CE‐FET with the CAAC/CAC‐OS structure can be fabricated using the existing amorphous silicon facilities and processes almost as they are. Therefore, we believe that high‐performance devices can be fabricated at low cost with large Gen 8‐10.5 glass substrates.

Fabrication of dynamic oxide semiconductor random access memory with 3.9 fF storage capacitance and greater than 1 h retention by using c-axis aligned crystalline oxide semiconductor transistor with L of 60 nm

A dynamic oxide semiconductor random access memory (DOSRAM) array that achieves reduction in storage capacitance (Cs) and decrease in refresh rate has been fabricated by using a c-axis aligned crystalline oxide semiconductor (CAAC-OS) transistor (L = 60 nm) with an extremely low off-state current. We have confirmed that this array, composed of cells that include a CAAC-OS transistor with W/L = 40 nm/60 nm using InGaZnO and a 3.9 fF storage capacitor, operates with write and read times of 5 ns. Therefore, DOSRAM can ensure sufficient Cs while maintaining operation speed comparable to that of dynamic random access memory (DRAM). We have found that the read signal voltage of DOSRAM is changed by approximately 30 mV after 1 h at 85 °C. Thus, DOSRAM is a promising replacement for DRAM.

Reflective liquid crystal display without flicker for reducing eye strain

AbstractWe fabricated two types of 6.05‐in. active matrix reflective liquid crystal displays (LCD) using a c‐axis‐aligned crystalline oxide semiconductor (CAAC‐OS) for the driver circuit and field‐effect transistors in pixels: one is of the high‐reflectance type, and the other is of the wide‐gamut type. Because of the small off‐state current of the CAAC‐OS and the improved liquid crystal material, low‐frequency driving at 1/60 fps or lower was achieved without memory in a pixel. Consequently, the still image display does not require data writing, except in turning pages; thus, it is flicker‐free in still image display. We also examined the page‐turning operation for less eye strain.The study shows that a reflective color LCD using a CAAC‐OS results in eye‐friendly still image display without flicker similar to an electrophoretic display (EPD); however, it is capable of moving image display, color display, and eye‐friendly page‐turning operation, which are difficult to achieve with an EPD.

Multilevel Cell Nonvolatile Memory with Field-effect Transistor Using Crystalline Oxide Semiconductor

As mobile terminals become more widely used and increasingly sophisticated, the amount of data processed continues to increase. This, in turn, increases the demand for high-speed high-capacity work memory. To meet this demand, various types of nonvolatile memory, such as resistive RAM, magnetoresistive RAM, and phase-change RAM, are under development. These types of nonvolatile memory are expected to have high speed equivalent to that of DRAM and high integration equivalent to that of NAND flash memory.A c-axis aligned crystalline oxide semiconductor (CAAC-OS) is an oxide semiconductor with crystals aligned in the c-axis direction. Use of a CAAC-OS in the active layer of an FET can provide extremely low off-state current [1]. Nonvolatile oxide semiconductor RAM (NOSRAM) using such a low off-state current has been reported [2]. A NOSRAM cell is composed of a CAAC-OS FET, a PMOS transistor, and a cell capacitor (Fig. 1). To hold charge accumulated in the capacitor of the NOSRAM cell, it is essential to prevent leakage from a node N. Such leakage is prevented by the CAAC-OS FET with ultra-low off-state current.To reduce the size of a NOSRAM cell, the CAAC-OS FET and cell capacitor are stacked on the PMOS transistor. The main features of a NOSRAM cell are as follows:i) An on/off ratio of approximately 107 (WL C = 0 V), which is obtained from I D-WL Ccharacteristics (Fig. 2), prevents read errors due to noise.ii) Endurance reaches 1012cycles (Fig. 3).iii) Because the NOSRAM cell accumulates charge, a multilevel cell (MLC) is achieved by controlling the amount of charge.iv) Controlling the amount of charge enables cell threshold voltages to be narrowly distributed at a high speed with high accuracy and without verify operations.v) In principle, unlimited write cycles are possible because the amount of charge is controlled by the CAAC-OS FET.However, the NOSRAM cell has more elements than other nonvolatile memory cells under development. NOSRAM already has a sufficiently high cell density, but its cell density needs to be further increased.This paper presents an MLC achieved using a CAAC-OS FET having extremely low off-state current. One property required for an MLC is cell threshold voltage distribution. With a narrow cell threshold voltage distribution, a memory cell can have more than one level. NOSRAM cell threshold voltages are distributed with 3σ = 100 mV [2]. A test chip of a scaled-down NOSRAM has a distribution with 3σ = 55 mV and achieves an 8-level cell (3 bits/cell) (Fig. 4) [3]. To achieve an MLC NOSRAM, a CAAC-OS FET with ultra-low off-state current is required to accurately control the amount of charge at the node N. A 4-bit/cell NOSRAM can have an ideal cell size of 4 F2or less per bit, where F is the feature size. Use of the CAAC-OS technology raises expectations for the feasibility of a 16-level cell.REFERENCES[1] Y. Sekine et al.: ECS Trans. 37(2011), pp. 77.[2] H. Inoue et al.: IEEE JSSC, 47(2012) pp. 2258.[3] S. Nagatsuka et al.: IMW, 2013, pp. 188.

3.3: Invited Paper: Future Possibility of C‐Axis Aligned Crystalline Oxide Semiconductors Comparison with Low‐Temperature Polysilicon

AbstractA C‐axis aligned crystalline oxide semiconductor (CAAC‐OS) has a crystal structure without grain boundaries and provides FETs with extremely low off‐state current. An ultrahigh‐resolution display using a CAAC‐OS is free from unevenness caused by grain boundaries. CAAC‐OSs use a small number of masks, and therefore can be easily applied to large‐substrate processes.

33.1: Channel‐Etched C‐Axis Aligned Crystalline Oxide Semiconductor FET Using Cu Wiring

AbstractA channel‐etched IGZO field‐effect transistor (FET) using Cu wiring was fabricated. Because little Cu is diffused into a c‐axis aligned crystalline oxide semiconductor (CAAC‐OS), which is c‐axis aligned crystalline IGZO, the use of the CAAC‐OS provides favorable characteristics for a channel‐etched FET.

44.1: Distinguished Paper: 13.3‐in. 8K x 4K 664‐ppi OLED Display Using CAAC‐OS FETs

AbstractWe have built a prototype of a 13.3‐inch 8k4k OLED display. The pixel density is 664 ppi. This display contains about 500,000,000 transistors and scan drivers integrated. We use c‐axis aligned crystalline oxide semiconductor (CAAC‐OS) FETs in the backplane of this display.

A normally-off microcontroller unit with an 85% power overhead reduction based on crystalline indium gallium zinc oxide field effect transistors

A low-power normally-off microcontroller unit (NMCU) having state-retention flip-flops (SRFFs) using a c-axis aligned crystalline oxide semiconductor (CAAC-OS) such as indium gallium zinc oxide (IGZO) transistors and employing a distributed backup and recovery method (distributed method) is fabricated. Compared to an NMCU employing a centralized backup and recovery method (centralized method), the NMCU employing the distributed method can be powered off approximately 75 µs earlier after main processing and can start the main processing approximately 75 µs earlier after power-on. The NMCU employing the distributed method can reduce power overhead by approximately 85% and power consumption by approximately 18% compared to the NMCU employing the centralized method. The NMCU employing the distributed method can retain data even when it is powered off, can back up data at high speed, and can start effective processing immediately after power-on. The NMCU could be applied to a low-power MCU.