Bus Signal Research Articles

Adaptive Sustainable Mobility Solutions by Using Vehicle-Integrated Photovoltaic in Kigali City

In a fast-paced urbanized culture, sustainable transportation remains a significant challenge. Quick and smooth mobility of people and goods with the possibility of regulating traffic congestion and preventing climate change is essential for every public transportation user. Urban population in developing nations like Rwanda is expected to double by the year 2050, and balancing the supply and demand of the urban transport system will be a significant issue. Information technology enables elements within the transportation system, including vehicles, roads, traffic lights, and message signs, to become intelligent by embedding them with sensors, processors, algorithms, and actuators, thus empowering them to communicate through various technologies. These technologies improve transportation system performance by reducing congestion, increasing safety and traveler convenience, and protecting the climate against some greenhouse gases. Different mobility solutions are stated in this document. The use of electric vehicles, Passenger Information Systems, Car-sharing and ride-sharing services, electronic payment, Bus Signal Priority, and Vehicle-Integrated Photovoltaics. Using photovoltaics in Rwanda is adequate because of the electricity problem. This is the best solution for fighting against climate change due to fuel from motorized traffic.

An Incorporated Power and Data Synchronous Transmission Method for SRG Integrated Wind Power Generation Systems

Reliable communication places important roles in renewable generation for operating status monitoring, fault alarming, cooperative control and so on. For existing power and data synchronous transmission strategies applied to switched reluctance generator (SRG) systems, the communication rate is limited by very low power switching frequencies. Hence, in this paper, a new PDST strategy is proposed and implemented in an SRG integrated wind generation system by incorporating power and data composite modulation method with signal injection method. For lower signal band, the data is modulated together with power by regulating the lower power switch of each phase in a fixed interval with given frequency, and for the higher signal band, the data in form of voltage ripple is injected into the bus by a coupling circuit. Therefore, specific voltage ripples with different given frequencies can be embedded into the power line for carrying signals, and the frequency band of signal bus can be well exploited. On signal receiver end, the voltage ripples are sampled and analyzed by fast Fourier transform method for demodulating the transmitted data. The feasibility of the proposed incorporated data transmission method is verified by experimental testing.

Dynamic Bus Scheduling Method Based on Mixed Control Strategy With Signal Timing Adjustment and Bus Holding

Dynamic Bus Scheduling Method Based on Mixed Control Strategy With Signal Timing Adjustment and Bus Holding

High-Linearity and High-Speed ROIC of Ultra-Large Array Infrared Detectors Based on Adaptive Compensation and Enhancement.

In order to solve the problem of limited linearity and frame rate in the large array infrared (IR) readout integrated circuit (ROIC), a high-linearity and high-speed readout method based on adaptive offset compensation and alternating current (AC) enhancement is proposed in this paper. The efficient correlated double sampling (CDS) method in pixels is used to optimize the noise characteristics of the ROIC and output CDS voltage to the column bus. An AC enhancement method is proposed to quickly establish the column bus signal, and an adaptive offset compensation method is used at the column bus terminal to eliminate the nonlinearity caused by the pixel source follower (SF). Based on the 55 nm process, the proposed method is comprehensively verified in an 8192 × 8192 IR ROIC. The results show that, compared with the traditional readout circuit, the output swing is increased from 2 V to 3.3 V, and the full well capacity is increased from 4.3 Me- to 6 Me-. The row time of the ROIC is reduced from 20 µs to 2 µs, and the linearity is improved from 96.9% to 99.98%. The overall power consumption of the chip is 1.6 W, and the single-column power consumption of the readout optimization circuit is 33 μW in the accelerated readout mode and 16.5 μW in the nonlinear correction mode.

A Bus Signal Priority Control Method Based on Deep Reinforcement Learning

To investigate the issue of multi-entry bus priority at intersections, an intelligent priority control method based on deep reinforcement learning was constructed in the bus network environment. Firstly, a dimension reduction method for the state vector based on the key lane was proposed, which contains characteristic parameters such as the bus states, the flow states, and the signal timing. Secondly, a control action method that can adjust phase sequence and phase green time at the same time was proposed under the constraints of maximum green and minimum green. Furthermore, a reward function, which can be uniformly converted into the number of standard cars, was established focusing on the indexes such as the busload and maximum waiting time. Finally, through building an experimental environment based on SUMO simulation, a real-time bus signal priority control method based on deep reinforcement learning was constructed. The results show that the algorithm can effectively reduce the waiting time of buses without affecting overall traffic efficiency. The findings can provide a theoretical basis for the signal control method considering bus priority and improve the operation efficiency of public transport.

Coordinated Control Method of Bus Signal Priority and Speed Adjustment Based on Stop-Skipping

There is an inherent coupling relationship between the time when buses arrive at the station and the time when they arrive the intersection, and it is essential to study the relationship as a whole to maximize the benefits of company operations and passenger services. In this study, a coordinated control method of signal priority and speed regulation in the stop-skipping mode at peak hours is proposed. First, the decision result of stop-skipping is obtained based on the historical passenger flow data. On this basis, the signal-priority decision is made for each vehicle in combination with the signal period and the arrival time of the intersection, and coordinated control is carried out in combination with the speed adjustment. The result of the genetic algorithm shows that cooperative control and prevention can minimize the passenger delay time and enterprise operation cost. The conclusions obtained in this research lay a theoretical foundation for company operation and signal-priority triggering mechanism.

Optimization model for bus priority control considering carbon emissions under non-bus lane conditions

Green extension and red truncation strategies were examined to study the influence of bus priority control strategies on traffic carbon emissions under non-bus lane conditions. Considering the main influencing factors, such as the delay and parking times, a bus speed probability density function based on the fluctuation characteristics of the vehicle speed in the intersection control area was introduced. A bus priority control optimization model was developed for non-bus lane conditions to optimize the carbon emission reductions of buses and social vehicles with different fuel types under different working conditions, and the Frank–Wolfe algorithm was used to solve the model. According to the model, when bus signal priority control was adopted under a green extension strategy, the carbon emission reductions were optimal (24.38%) when the green extension was 6 s. Under a red truncation strategy, the carbon emission reductions were optimal (26.01%) when the red truncation was 5 s. These results suggest ways in which carbon emissions in the intersection control area can be reduced to achieve the optimal overall traffic benefit for the intersection.

An Online Optimal Bus Signal Priority Strategy to Equalise Headway in Real-Time

Bus bunching is a severe problem that affects the service levels of public transport systems. Most of the previous studies in the field of Bus Signal Priority (BSP) and Transit Signal Priority (TSP) focus on reducing a bus delay at signalised intersections and ignore the importance of balancing the bus headways. However, since general BSP methods allocate uneven priorities for individual buses, the headways of bus sequences are prioritised or delayed randomly, increasing the likelihood of bus bunching. To address this problem and to improve the reliability of bus services, we propose an online optimisation model to determine the signal duration and splits for each traffic intersection and each signal cycle for bus priority. The proposed model is able to induce the signal timing back to a baseline when the BSP request frequency is low. Using the proposed model, a statistically significant reduction of 10.0% was achieved for bus headway deviation and 6.4% for passenger waiting times. The simulation-based evaluation results also indicate that the proposed model does not affect the efficiency of bus services and other vehicles significantly.

Study of Photodetectors with Schottky Barriers Based on the IrSi–Si Contact

A significant increase in the fill factor of Schottky matrices is achieved by reading the charge accu-mulated in the Schottky diode not by using charge-coupled device (CCD) registers but by injecting it into the signal bus, similarly to charge-injected device (CID) structures on narrow-gap semiconductors. In this case, the multielement matrix contains horizontal buses to poll the elements of the selected row, vertical signal lines, and a metal–oxide–semiconductor (MOS) switch for connecting the polled column and the matrix of photosensitive elements, each consisting of a photosensitive Schottky diode and a MOS switch.

Testing of AMBA AXI Protocol

The rapidly expanding VLSI sector has a great need for a very robust verification mechanism that can be developed in a short amount of time in the constantly changing environment where new intellectual property and chips are being designed every day having reduced time-to-market. (SoC) System on Chip design emerged as a primary integrated technique for reducing the design time of the entire system with the introduction of a standardized signal bus architecture used for the connectivity of different modules of the system. One of the major difficulties at hand is how to check these on chip bus protocols, since traditional old methods are ineffective in certifying large SoCs. In this paper, we have verified AMBA AXI protocol which shows write as well as read operations using System Verilog. Keywords: AMBA AXI, APB, AHB.

A Review on Bus Signal Priority Systems

A Review on Bus Signal Priority Systems

Analysis of Bus Signal Priority Effect by BRT Stop Types: Focusing on Hannuri-daero, Sejong

Analysis of Bus Signal Priority Effect by BRT Stop Types: Focusing on Hannuri-daero, Sejong

A Bus Signal Priority Model at Oversaturated Intersection under Stochastic Demand

This paper focuses on the optimization of bus signal priority with the consideration of the stochastic traffic demand. Based on a situation of the variability of traffic composition, the phase clearance reliability (PCR) value of each phase and traffic composition ratio is introduced to reflect the traffic condition at intersection. Then, a bus signal priority optimization model is proposed with the purpose of the maximum of the total vehicular departure as the optimization goal. In order to obtain the optimal solution, an improved algorithm is designed by introducing the PCR value search strategy. Finally, two cases’ study is exhibited to demonstrate the reasonability of the model, theory, and algorithm. The result shows that the model can not only clear the queue under the condition of continuous dynamic traffic flow but also reduce the vehicle queuing and passenger delay.

An integrated intersection design for promoting bus and car traffic

Signal priority and exclusive bus lanes are common measures used to promote bus travel at signalized intersections. However, these bus priority measures create significant damage to the car traffic especially at intersections with heavy bus and car traffic. For this reason, bus priority is not welcome at busy intersections. We examine a novel intersection approach design that can solve the above dilemma. The design integrates a bus lane, bus signal priority, and a midblock pre-signal for sorting different car traffic streams in tandem in the approach. Car capacity gains from the use of pre-signal can potentially recover the car capacity lost to bus lane and signal priority schemes. This paper first presents how the pre-signal and main signal can be timed to realize bus signal priority, and where the pre-signal should be placed. Models are then formulated for estimating the expected bus delay and car capacity under the integrated design. They are compared against three alternative designs, including a conventional intersection design without bus priority or pre-signal. Numerical results unveil that the integrated design produces not only significant bus delay savings, but also higher car capacities in most instances. Even greater car capacity gains are observed with higher bus frequencies. Moreover, the benefits are fairly robust when real-world operating features, such as bus arrival time prediction error, are considered. Thus, the integrated design can potentially promote both bus and car traffic at congested intersections.

An Overlapping Phase Approach to Optimize Bus Signal Priority Control under Two-Way Signal Coordination on Urban Arterials

With the consideration of the uneven traffic volume distribution at intersections on urban arterials, this paper aims to minimize the overall passenger delay (buses and private vehicles) at intersections and identify the applicable conditions of the proposed method with field data. The overlapping phase-based signal control logic and the bus priority control algorithm under two-way signal coordination on arterial roads are proposed. The vehicular capacities and occupancies for buses and passenger cars are considered in the evaluation of the method performance. A field test was carried out at two major intersections on an arterial road in Hefei, China. With the test data, the proposed method is examined and the possible influencing factors are analyzed for identifying the corresponding applicable conditions. The analysis result shows that the application of the overlapping phase helps to provide a relatively flexible signal control for the varying traffic demands at intersections. Compared to the conventional phase, it isof more practical significance to consider overlapping phase and apply bussignal priority control under two-way signal coordination according to the condition of uneven traffic volumedistribution at intersections on urban arterials. The proposed method can effectively decrease the total passenger delay at the intersections on urban arterials under certain applicable conditions. The possible factors influencing the method applicability are identified as well. It is verified that bus signal priority control under the two-way signal coordination, based on overlapping phases, is more conducive to improving traffic efficiency on urban arterials. Regarding the influencing factors and the applicability of the proposed method, the results show that not all situations are conducive to decreasing passenger delay at intersections. The proposed method should be applied under certain applicable conditions and principles in order to efficiently and effectively improve the traffic efficiency on arterial roads.

An analytical approach to real-time bus signal priority system for isolated intersections

Bus signal priority (BSP) is an active traffic management measure to reduce bus travel delay at signalized intersections and to improve the bus service reliability. In this paper, we present a real-time BSP system with a primary focus on its practical implementation. We tackle two inter-related issues of existing priority systems, namely, real-time computation and solution optimality, using an analytical approach. The core of the proposed priority system involves two signal controller actions – red truncation (RT) and green extension (GE), which determine the priority timings based on the objective of minimizing total person delay incurring at the subject intersection. We demonstrate the analytical approach by deriving closed-form expressions for optimal RT and GE for a two-phase signal using cumulative count curves. The inputs required for these priority models are based on average traffic and bus conditions limited to the current signal cycle alone. Solutions for the RT and GE models indicate that three dimensionless variables – ratio of bus-arrival time to traffic queuing time, ratio of bus passenger occupancy to other vehicles’ average passenger occupancy, and ratio of traffic demand to saturation flow ratio – govern the priority decisions. Simulation results showed significant delay reduction for buses (≈22%) with a negligible impact on other traffic users during low to medium traffic conditions and high bus frequencies (3 min headway).

Dynamic Thresholds Identification for Green Extension and Red Truncation Strategies for Bus Priority

Among the different strategies adopted to improve the efficiency and reliability of the bus services, bus signal priority is a low cost and less infrastructure- demanding solution that has the potential to reduce bus travel times in urban arterials. This paper develops analytical models for finding the thresholds for Green Extension (GE) and Red Truncation (RT) for a four-phase signal system with buses on conflicting phases. The thresholds are developed based on reducing the total person delay after considering buses from the current cycle and unserved buses from the previous cycle for priority decisions. The proposed models aim for zero-delay service for the buses from the current cycle and reducing delay for the unserved buses from the previous cycle. The models reveal that at multi-phase signals, several bus priority alternatives are possible to reduce total person delay and agencies can choose alternatives based on their requirements and constraints. These models are evaluated in VISSIM microscopic simulation environment. The evaluation results indicate a 16.7 to 42.8% reduction in total person intersection delay due to the implemented bus priority.

Improving schedule adherence based on dynamic signal control and speed guidance in connected bus system

Purpose The purpose of this paper is to develop a dynamic control method to improve bus schedule adherence under connected bus system. Design/methodology/approach The authors developed a dynamic programming model that optimally schedules the bus operating speed at road sections and multiple signal timing plans at intersections to improve bus schedule adherence. First, the bus route was partitioned into three types of sections: stop, road and intersection. Then, transit agencies can control buses in real time based on all collected information; i.e. control bus operating speed on road sections and adjust the signal timing plans through signal controllers to improve the schedule adherence in connected bus environment. Finally, bus punctuality at the downstream stop and the saturation degree deviations of intersections were selected as the evaluation criteria in optimizing signal control plans and bus speeds jointly. Findings An illustrative case study by using a bus rapid transit line in Jinan city was performed to verify the proposed model. It revealed that based on the proposed strategy, the objective value could be reduced by 73.7%, which indicated that the punctuality was highly improved but not to incur excessive congestion for other vehicular traffic. Originality/value In this paper, the authors applied speed guidance and the adjustment of the signal control plans for multiple cycles in advance to improve the scheduled stability; furthermore, the proposed control strategy can reduce the effect on private traffics to the utmost extend.

Online Detection of Aircraft ARINC Bus Cable Fault Based on SSTDR

In order to realize the online detection of ARINC bus cable fault, a method of spread spectrum time-domain reflectometry (SSTDR) is proposed in this article, which can minimize the influence between the ARINC bus signal and incident signal, and meet the requirements of aircraft airworthiness. First, the impedance characteristics and reflection characteristics of the aircraft ARINC bus cables are analyzed so that the online detection model based on SSTDR is constructed. Then, the SSTDR incident signal is designed by studying the relationship between the incident signal parameters and the ARINC bus characteristics. Finally, the proposed method is verified through the online detection platform of ARINC 429/825 bus cable fault, and the experimental signals are analyzed in the time domain and the frequency domain, respectively, which indicates that the ARINC bus signal and the incident signal do not interfere with each other. The experimental results prove that the method of SSTDR is effective and feasible to the online detection of ARINC bus cable fault.

Design of Advanced High Performance Bus Tracer in System on Chip Using Matrix Based Compression for Low Power Applications

This project proposes multilayer advanced high-performance bus architecture for low power applications. The proposed AHB architecture consists of the bus arbiter and the bus tracer (A.R.M.A., 1999. Specification (Rev 2.0) ARM IHI0011A). The bus arbiter, which is self motivated selects the input packet based on the control signals of the incoming packet. So that arbitration leads to a maximum performance. The On-Chip bus is an important system-on-chip infrastructure that connects major hardware components. Monitoring the on-chip bus signals is crucial to the SoC debugging and performance analysis/optimization (Gu, R.T., et al., 2007. A Low Cost Tile-Based 3D Graphics Full Pipeline with Real-Time Performance Monitoring Support for OpenGL ES in Consumer Electronics. 2007 IEEE International Symposium on Consumer Electronics, June; IEEE. pp.1–6). But, such signals are difficult to observe since they are deeply embedded in a SoC and there are often no sufficient I/O pins to access these signals. Therefore, a straightforward approach is to embed a bus tracer in SoC to capture the bus signal trace and store the trace in on-chip storage such as the trace memory which could then be off loaded to outside world for analysis. The bus tracer is capable of capturing the bus trace with different resolutions, all with efficient built in compression mechanisms such as dictionary based compression scheme for address and control signals and differential compression scheme for data. To improve the compression ratio matrix based compression which is lossless compression is used instead of differential compression. This system is designed using Verilog HDL, simulated using Modelsim and synthesized using Xilinx software.