Bulk Trap Generation Research Articles

Insights Into the Effect of TiN Thickness Scaling on DC and AC NBTI Characteristics in Replacement Metal Gate pMOSFETs

Fast characterization methods are utilized to investigate DC and AC negative bias temperature instability (NBTI) characteristics in pMOSFETs with different TiN capping layer thicknesses ( ${t} _{\mathrm{ TiN}}$ ). The impacts of ${t} _{\mathrm{ TiN}}$ scaling on the threshold voltage shift ( ${\Delta }\text{V}_{\mathrm{ T}}$ ), pre-existing hole traps ( ${\Delta }\text{V}_{\mathrm{ HT}}$ ), generated traps (GTs), and their relative contributions are studied. The time exponents of ${\Delta }\text{V}_{\mathrm{ T}}$ and GTs, and the impacts of stress voltage, temperature, frequency, and duty cycle on the NBTI degradation are analyzed. DC and AC NBTI degradations increase with ${t} _{T}{}_{iN}$ . When ${t} _{\mathrm{ TiN}}$ is scaled down from 3 nm to 1 nm, the maximum operation field is improved by 60%, which originates from the reduction in both ${\Delta }\text{V}_{\mathrm{ HT}}$ and GTs. Moreover, we experimentally demonstrate that bulk trap generation is an ${f}$ -dependent process and that its relative contribution to ${\Delta }\text{V}_{\mathrm{ T}}$ increases with ${t} _{\mathrm{ TiN}}$ , which is an important factor for the improvement of NBTI through ${t} _{\mathrm{ TiN}}$ scaling.

Understanding Frequency Dependence of Trap Generation Under AC Negative Bias Temperature Instability Stress in Si p-FinFETs

In this letter, we present an experimental study on the frequency ( f ) dependence of trap generation under AC negative bias temperature instability (NBTI) stress in Si p-channel fin field-effect transistors (p-FinFETs), by adopting the direct-current current voltage (DCIV) method and an energy profiling technique. The interface trap generation ( $\Delta ~\text{N}_{IT}$ ) and bulk trap generation ( $\Delta ~\text{N}_{OT}$ ) are separated from the measured DCIV data and their ${f}$ dependences are independently investigated. The DCIV results indicate that the observed strong ${f}$ dependence of trap generation is primarily attributed to the ${f}$ -dependent $\Delta ~\text{N}_{OT}$ that exhibits a 36% reduction when ${f}$ increases from 10 Hz to 1 MHz. Furthermore, this ${f}$ -dependent $\Delta ~\text{N}_{OT}$ is mainly distributed between ${\text{E}_{v}}$ and ${\text{E}_{i}}$ , and exhibits a visible ${f}$ -dependent peak of energy density around ${\text{E}_{c}}$ .

A Comparative Analysis of NBTI Variability and TDDS in GF HKMG Planar p-MOSFETs and RMG HKMG p-FinFETs

The time kinetics of threshold voltage shift ( $\Delta {V}_{T}$ ) is measured for negative-bias temperature instability (NBTI) and time-dependent defect spectroscopy (TDDS) experiments by an ultra-fast (10- $\mu \text{s}$ delay) method in gate-first high- ${k}$ metal gate (HKMG) planar p-MOSFETs and replacement metal gate HKMG p-FinFETs. The mean NBTI stress-recovery time kinetics obtained from multiple small-area MOSFETs and few-fin FinFETs at different values of stress bias ( ${V}_{\text {GSTR}}$ ) and temperature ( ${T}$ ) is modeled by uncorrelated contributions from interface ( $\Delta {V}_{\text {IT}}$ ) and bulk ( $\Delta {V}_{\text {OT}}$ ) trap generation and trapping of holes ( $\Delta {V}_{\text {HT}}$ ) in pre-existing defects. The time constant associated with recovery steps and the impact of each step for multiple TDDS sweeps on a single device and after NBTI in multiple devices are compared. The NBTI-induced $\Delta {V}_{T}$ distribution shape is verified using TDDS charge impact. The shift in mean and variance of NBTI-induced $\Delta {V}_{T}$ and post-stress ${V}_{T}$ distributions is modeled.

(Invited) Negative-Bias Temperature Instability – Insight from Recent Dynamic Stress Experiments

The purpose of this paper is to summarize key experimental evidences on the important role of hole trapping on negative-bias temperature instability (NBTI). For a long time, the focus of this research topic had been on interface degradation driven by hydrogen transport and hole trapping was regarded as a side effect arising out of fast measurement techniques proposed to mitigate the effect of recovery on measurement data. In recent studies, we showed that the threshold voltage (V t) fluctuations one typically observed under dynamic NBTI were mainly the result of hole trapping and not hydrogen-transport driven interface-state generation/passivation proposed earlier. In particular, the cyclical V t shifts and constant V t recovery are inconsistent with the basic principle of the hydrogen transport model. Such behaviors are better described in terms of hole trapping/detrapping at pre-existing oxide defects. We have also shown that interface degradation during NBTI stressing has no apparent impact on bulk (oxide) trap generation, i.e. interface trap generation does not lead to bulk trap generation. This result raises further questions on the validity of the hydrogen transport mechanism and the long standing hypothesis on hydrogen-induced bulk trap generation and gate oxide breakdown. Finally, it is shown that the transient hole trapping responsible for the V t shift fluctuations could be transformed into more permanent trapped holes under NBTI stressing. The extent of transformation is accelerated by a high oxide field and temperature. An excellent correlation with stress induced leakage current indicates that such transformation underlie the generation of bulk traps reported by earlier studies.

Evolution of Hole Trapping in the Oxynitride Gate p-MOSFET Subjected to Negative-Bias Temperature Stressing

We present experimental evidence of a thermally activated transformation of negative-bias-temperature-stress-induced transient hole trapping at preexisting oxide traps into more permanent trapped holes in the ultrathin oxynitride gate p-MOSFET. The transformation is also shown to correlate with the generation of stress-induced leakage current, indicating that it is one of the key mechanisms of bulk trap generation. A similar observation (reported elsewhere) applies to the HfO2 gate p-MOSFET, implying that the observed hole-trap transformation is a common mechanism for bulk trap generation across different gate oxide technologies. The results further imply that preexisting oxide defects, usually deemed irrelevant to negative-bias temperature instability, have a definite role on long-term device parametric drifts.

Bulk and interface trap generation under negative bias temperature instability stress of p-channel metal-oxide-semiconductor field-effect transistors with nitrogen and silicon incorporated HfO2 gate dielectrics

Negative bias temperature instabilities (NBTIs) of p-channel metal-oxide-semiconductor field-effect-transistor with HfO2, HfOxNy, and HfSiON were investigated. Higher bulk trap generation (ΔNot) is mainly attributed to threshold voltage shift rather than interface trap generation (ΔNit). ΔNit, ΔNot, activation energy (Ea), and lifetime were exacerbated with incorporated nitrogen while improved with adding Si into gate dielectrics. Compared to HfO2, HfOxNy showed worse NBTI due to nitrogen pile-up at Si interface. However, adding Si into HfOxNy placed nitrogen peak profile away from Si/oxide interface and NBTI was reduced. This improvement is ascribed to reduced ΔNot and ΔNit, resulting from less nitrogen at Si interface.

Electrical and Reliability Studies of “Wet $ \hbox{N}_{2}\hbox{O}$” Tunnel Oxides Grown on Silicon for Flash Memory Applications

In this paper, we report the electrical characteristics and reliability studies on tunnel oxides fabricated by wet oxidation of silicon in an ambient of water vapor and N2O at a furnace temperature of 800 degC. Tunnel oxides that have an equivalent oxide thickness of 67 A are subjected to a constant-current stress (CCS) amount of -100 mA/cm2 using a MOS capacitor to obtain information on stress-induced leakage current (SILC), interface, and bulk trap generation. The obtained results clearly demonstrate the superior performance features of the present tunnel oxides with reduced SILC, lower trap generation, minimum change in gate voltage, and higher charge-to-breakdown during CCS studies. X-ray photoelectron spectroscopy depth profile studies of the tunnel oxide interfaces have shown that the improved performance characteristics and reliability can be attributed to the incorporation of about 8.5% nitrogen at the oxide-silicon interface of the samples formed by the wet process that involves low-temperature oxidation and annealing at 800 degC.

NEGATIVE BIAS TEMPERATURE INSTABILITY IN TIN/HF-SILICATE BASED GATE STACKS

This work studies the effects of negative bias temperature instability (NBTI) on p-channel MOSFETS with TiN/HfSi x O y (20% SiO 2 based high-κ gate stacks under different gate bias and elevated temperature conditions. For low bias conditions, threshold voltage shift (ΔVT) is most probably due to the mixed degradation within the bulk high-κ. For moderately high bias conditions, H-species dissociation in the presence of holes and subsequent diffusion may be initially responsible for interface state and positively charged bulk trap generation. Initial time, temperature and oxide electric field dependence of ΔVT in our devices shows an excellent match with that of SiO 2 based devices, which is explained by reaction-diffusion (R-D) model of NBTI. Under high bias condition at elevated temperatures, due to higher Si - H bond-annealing/bond-breaking ratio, the experimentally observed absence of the impact ionization induced hot holes at the interfacial layer (IL)/ Si interface probably limits the interface state generation and ΔVT as they quickly reach saturation.

NBTI Effects in pMOSFETS with TiN/Hf-Silicate Based Gate Stacks

Effects of negative bias temperature instability (NBTI) on p-channel MOSFETS with TiN/HfSixOy (20% SiO2) based high-k gate stacks are studied under different gate bias and elevated temperature conditions. For low bias conditions, threshold voltage shift (Delta VT) is most probably due to the mixed degradation within the bulk high-k. For moderately high bias conditions, H-species dissociation in the presence of holes and subsequent diffusion may be initially responsible for interface state and positively charged bulk trap generation. Initial time, temperature and oxide electric field dependence of Delta VT in our devices conform to SiO2 based reaction-diffusion (R- D) model of NBTI. Under high bias condition at elevated temperatures higher Si-H bond-annealing/bond-breaking ratio, due to the experimentally observed absence of the impact ionization induced hot holes at the interracial layer (IL)/Si interface, probably limits the interface state generation and Delta VT as they quickly tend to saturate.

Evidence for bulk trap generation during NBTI phenomenon in pMOSFETs with ultrathin SiON gate dielectrics

Negative bias temperature instability (NBTI) of pMOSFETs with direct-tunneling SiON gate dielectrics was studied in detail. By investigating the effects of applying positive gate bias on pMOSFETs after exposure to NBT stress, the generation of bulk charge traps in the gate dielectrics during NBTI was clearly demonstrated. In particular, it was found that a positive charge generated by negative bias temperature stress (NBT stress) can be neutralized and that the neutralized site can return to the positive state. We consider that the bulk trap is due to hydrogen atoms released from the interface between the SiON gate dielectric and the Si substrate (and this is what has conventionally been considered a positive fixed charge). Moreover, the bulk trap generation was shown to give rise to stress-induced leakage current.

Negative Bias Temperature Instability in CMOS Devices

This paper reviews the experimental and modeling efforts to understand the mechanism of Negative Bias Temperature Instability (NBTI) in p-MOSFETs, which is becoming a serious reliability concern for analog and digital CMOS circuits. Conditions for interface and bulk trap generation and their dependence onstress voltage and oxide field, temperature and time are discussed. The role of inversion layer holes, hot-holes and hot-electrons are also discussed. The recovery of generated damage and its bias, temperature and AC frequency dependence are discussed. The degradation and recovery is modeled using the standard Reaction-Diffusion theory, and some unique data scaling features are pointed out. The impact of gate-oxide nitridation is also reviewed.

Investigation and Modeling of Interface and Bulk Trap Generation During Negative Bias Temperature Instability of p-MOSFETs

Negative bias temperature instability is studied in thick and thin gate oxide p-MOSFETs. The relative contributions of interface- and bulk-trap generation to this device degradation mode are analyzed for a wide range of stress bias and stress temperature. The effects of gate voltage and oxide field, as well as those of inversion layer holes, impact ionized hot holes, and hot electrons on interface- and bulk-trap generation, are identified. The bulk-trap generation process is interpreted within the modified anode-hole injection model and the mechanism of interface-trap generation is modeled within the framework of the classical reaction-diffusion theory. The diffusion species for interface-trap generation is unambiguously identified. Moreover, a high-temperature, diffusion-triggered, enhanced interface-trap generation mechanism is discussed for thin gate oxide p-MOSFETs. Finally, a novel scaling methodology is proposed for interface-trap generation that helps in obtaining a simple, analytical model useful for reliability projection.

Characterization of ultrathin oxynitride (18-21 A) gate dielectrics by NH/sub 3/ nitridation and N/sub 2/O RTA treatment

In this paper, we developed a new method to grow robust ultrathin oxynitride (E/sub OT/=18 A) film with effective dielectric constant of 7.15. By NH/sub 3/-nitridation of Si substrate, grown ultrathin Si/sub 3/N/sub 4/ With N/sub 2/O annealing shows excellent electrical properties in terms of significant lower leakage current, very low bulk trap density and trap generation rate, and high endurance in stressing. In addition, this oxynitride film exhibits relatively weak temperature dependence due to a Fowler-Nordheim (FN) tunneling mechanism. This dielectric film appears to be promising for future ultralarge scale integrated (ULSI) devices.

Electrical characterization of metal–oxide–semiconductor capacitors with anodic and plasma-nitrided oxides

We have studied two novel techniques that should inherently be more uniform than current mainstream processes used to produce silicon dioxide or nitrided-oxide gate insulators. Anodic films were fabricated by anodizing Si wafers in HCl solutions, and thermal oxide films were nitrided in N2O plasmas produced with an electron-cyclotron resonance source. Using typical polysilicon-gate test structures, the electrical characteristics are obtained and compared to thermal oxides. Both techniques can produce thin films (<15 nm thick) with interface state densities and leakage currents initially comparable to their thermal oxide counterparts, if the films are subjected to rapid thermal annealing at temperatures of 950 °C. The annealed films are subjected to high-field (⩾8 MV/cm) Fowler–Nordheim stress and the buildup of trapped charge is monitored as a function of time. Anodic films are found to have moderately higher bulk and interface trap generation rates than the thermal control. Thinner anodic oxides, which were grown at slower rates, had better properties than thicker anodic oxides, suggesting that even slower growth rates could yield anodic oxides with improved electrical properties.

Charge trap generation in LPCVD oxides under high field stressing

The degradation of low pressure chemical vapor deposited (LPCVD) oxides, prepared using silane and tetra ethyl ortho silicate (TEOS) as the source, has been investigated under high field stressing. The LPCVD oxides exhibit enhanced conductivity for the Fowler-Nordheim tunneling current, which is modeled as an effective lowering of potential barrier at the injecting electrode. The charge to breakdown (Q/sub bd/) of LPCVD oxides depends on both the deposition chemistry and post deposition annealing condition. The change in interface-state density (/spl Delta/D/sub it/), flatband voltage (/spl Delta/V/sub fb/), and gate voltage (/spl Delta/|V/sub g/|) during constant current stressing are studied to identify the degradation mechanism. We see a very good correlation between Q/sub bd/ and /spl Delta/|V/sub g/|, indicating that the degradation in LPCVD oxides is dominated by bulk trap generation and subsequent charge trapping. We present a detailed theoretical analysis to substantiate this.

Voltage and Fluence Dependence of Stress‐Generated Traps inside Thin Silicon Oxide

The density of traps generated inside of thin has been calculated by measuring the transient discharge of the traps and applying the tunneling front model to these discharges. The number of traps created by the high voltage stress was proportional to the cube root of the fluence that flowed through the oxide during the stress. The trap generation rate varied as the . As was the case with interface trap generation, there was a voltage dependence to the bulk trap generation. The bulk trap generation was comparable in magnitude to the interface trap generation. The trap generation results were used to generate simulated time‐dependent dielectric breakdown data using a model of dielectric breakdown based on random generation of traps inside the oxide. The simulated breakdown distributions agreed well with measured distributions.

Oxide thickness dependence of interface trap generation in a metal-oxide-semiconductor structure during substrate hot-hole injection

Oxide thickness dependence of interface trap generation in a metal-oxide-semiconductor (MOS) structure is investigated using uniform hot-hole injection into the gate oxides of p-channel MOS transistors with very thin oxide thicknesses. Significant dependence of interface trap generation on oxide thickness (tox) is found for very thin oxides and the dependence disappears for tox≥8 nm. A universal relationship between hole trapping in the oxide bulk and interface trap generation at the Si/SiO2 interface is observed experimentally. The experimental results suggest that interface trap generation is a process involving hole trapping in the oxide bulk, rather than a pure interfacial process. No oxide thickness dependence of interface trap generation for thicker oxides (tox≥8 nm) is in agreement with previous reports and the overall dependence can consistently be explained with the help of the spatial distribution of trapped holes in the oxide. In contrast to the reports describing delayed interface trap formation, we observed oxide field-dependent annealing of the generated interface traps after the end of hole injection.

Interface and bulk trap generation in metal-oxide-semiconductor capacitors

The effects of electron-hole pair recombination near the silicon/silicon dioxide interface of aluminum-gate metal-oxide-semiconductor capacitors have been studied. For the first time, electron-heating-induced trap generation and interface state creation is separated from those defects created through electron-hole pair recombination. The midgap interface state density is observed to increase linearly with the number of recombination events and approaches saturation in the mid 1011 eV−1 cm−2 range for trapped hole densities greater than about 1012 cm−2. However, the total integrated interface state density, although showing a similar net increase to that of the midgap interface state density, does not saturate for the largest trapped hole densities introduced in this work. For hot-electron-induced defects, a dramatic increase in the interface state generation rate is observed for average electric fields above a threshold of 1.5×106 V cm−1. An increase in the electron trapping rate above the heating threshold is also detected at both the cathode and anode interfaces. The rate is found to be approximately 10−5 traps or interface states generated per injected electron for average electric fields below the heating threshold, while above the threshold this rate increases by an order of magnitude. These rates were measured for injected electron fluences as low as 10−3 C cm−2. These high trapping and interface state generation rates are believed to be due to the high concentration of hydrogen (or hydrogen-related species) in these films.

The effect of hydrogen on trap generation, positive charge trapping, and time-dependent dielectric breakdown of gate oxides

The effect of high-temperature ( approximately=900 degrees C) hydrogen on the gate oxides of MOS devices is studied. Hydrogen is introduced into devices by either high-temperature anneal or conventional process steps such as low-pressure chemical vapor deposition (LPCVD) of Si/sub 3/N/sub 4/. In all cases, measurements of high-field stress behavior show that high-temperature hydrogen steps reduce time to breakdown and increase bulk and interface trap generation, but do not affect the generation of positive charge. These results indicate that the wear-out mechanism of gate oxides at high fields is related to trap generation rather than to accumulation of positive charge.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Non-equilibrium ψs vs Vg characteristics of MOS capacitors and related effects

A new method for measuring the non-equilibrium surface potential of an MOS capacitor as a function of gate voltage is described. The system response is related to the bulk trap generation rate, and the technique is then used for finding generation rate at various surface potentials and, hence, depletion widths. Using this value of generation rate in the theoretical ψ s vs V g equation, results in curves that are in excellent agreement with the experimental results. The generation rate is then used to obtain the theoretical IV characteristics of the capacitor subjected to a constant voltage ramp. These characteristics are also found to be in excellent agreement with corresponding experimental characteristics. Finally, the observed anomalous behaviour of the quasi-static section of the reverse sweep curve of the ψ s vs V g plots is explained using a p- n junction analogy.