Bulk-driven OTA Research Articles

0.35 V Subthreshold Bulk-Driven CMOS Second-Generation Current Conveyor

This study describes a high-performance second-generation Current Conveyor (CCII) operating at 0.35 V and achieving rail-to-rail operation at the Y terminal and class AB current drive at the X and Z terminals. The solution utilizes a low-voltage subthreshold bulk-driven CMOS OTA that was experimentally developed earlier, making systematic use of body terminals to improve small-signal and large-signal performance. The circuit has a high open-loop voltage gain and uses cascoded current mirror topologies, resulting in precise voltage and current transfer with bandwidths of 1.33 MHz and 2.13 MHz, respectively. The CCII offers a linear current drive up to 2.5 µA while consuming a total quiescent current of 2.86 µA (758 nA in the output branches), displaying one the highest figures of merit in terms of current utilization for sub 1 V solutions.

0.5-V High Linear Fully Differential Multiple-Input Bulk-Driven OTA With Effective Self-Embedded CMFB

0.5-V High Linear Fully Differential Multiple-Input Bulk-Driven OTA With Effective Self-Embedded CMFB

31.3 nW, 0.5 V Bulk-Driven OTA for Biosignal Processing

31.3 nW, 0.5 V Bulk-Driven OTA for Biosignal Processing

High current efficiency fast transient gain-boosted single-stage bulk-driven OTA with enhanced input stage suitable for heavy capacitive loads

This article presents a 0.5 V operated, bulk-driven subthreshold OTA with up to 30 nF capacitive load driving capability. The input stage utilizing three unmatched pseudo-differential pairs is biased with two DC level shifters, especially bulk-driven flipped voltage followers in a direct and cross-coupled connection, exhibiting superior performance to existing bulk-driven OTAs. The input transconductance stage with local common-mode feedback (LCMFB) followed by partial positive feedback (PPF) contributes a large dynamic output current using three-successive amplification. As a result, the proposed OTA provides 24.2 times higher effective input core transconductance, 2.62 times higher DC gain, and 11.5 times more slew rate than a conventional class-A BD OTA with PPF at 5% lower static power. The post-layout results of the proposed OTA for a 10 nF capacitive load using UMC 0.18-µm technology in Cadence Virtuoso-XL yield a DC gain of 124.6 dB, a UGF of 183.47 kHz, a PM of 89.98°, and greater figures of merit (FOM) for small- and large-signal performance than the state-of-the-art bulk-driven OTAs.

Low power bulk-driven OTA design optimization using cuckoo search algorithm

The design of CMOS analog integrated circuits presents low level of automation and still depends on the experience of the designer. The sizing procedure for low power applications is challenging, since transistors must be biased in the sub-threshold region, whose modeling is complex and few intuitive if second order effects in sub-micron technologies are considered. This paper presents an automatic design methodology for a 0.25 V bulk-driven Miller OTA in 130 nm CMOS using bioinspired cuckoo search optimization technique implemented in the UCAF tool, which is able to explore efficiently the design space in all transistor operating regions, particularly weak inversion region. The methodology also includes the estimation of circuit performance under process parameter variation. The resulting sized circuit presented better performance if compared to a manual design, achieving a power consumption of 8.47 nW and a gain-bandwidth product of 1.61 kHz. We demonstrate in this work that an efficient search in the design space with an analog CAD tool can result in optimized circuits that demand transistors operating in sub-threshold region.

Low-power Bulk-driven Subthreshold OTA and CCII+ Cells based Instrumentation Amplifier for LF Applications

This paper at onset describes a low-power, bulk-driven, folded cascode (FC-OTA) and second generation positive current conveyor (CCII+) operating in weak inversion region with ± 0.35 V DC bias supply. The designed 2 or 3 numbers of CCII+ cells are utilized to compose an instrumentation amplifier (IA), which dissipates a total power of 3.847 µW or 5.768 µW. The OTA cell as the input core in CCII+ circuitry consumes a power of 287 nW, whereas the CCII+ cell consumes total power of 1918 nW. The CCII+ cell uses an OTA which is followed by two-CMOS class AB inverters to realize the X and Z terminals of CCII+ cell. Further, these CCII+ cells are utilized to get low power IA usable in analog front ends of DSP processor for amplifying sensed signal with very high-common mode rejection ratio (CMRR) and high-power supply rejection ratio (PSRR). This IA is simulated using tanner EDA tool of version 16.1 in 180 nm n-tub standard CMOS process technology. This IA consumes less power and is usable as variable gain amplifier for low- frequency bio-signal as well as sub-audio frequency range signal processing.

0.5 V sixth-order Chebyshev band-pass filter based on multiple-input bulk-driven OTA

This paper presents a low-voltage sixth-order Chebyshev band-pass filter based on multiple-input operational transconductance amplifier (MI-OTA). The used voltage supply is 0.5 V and the filter employs six MI-OTAs and six capacitors. The third intermodulation distortion (3rd IMD) is below 1% for input sine wave signal with peak-to-peak up to rail-to-rail while the dynamic range (DR) is 66.8 dB. In order to insure low-voltage operation capability, extended linear range, increased voltage gain of the MI-OTA, the multiple-input bulk-driven transistor (MIBD) along with self-cascode techniques have been used. As a result, the proposed MI-OTA based on MIBD is capable to work with 0.5 V supply voltage and consumes power in the range of (2.5–1.2E3) nW for tunable bias current in the range from 1 nA to 500 nA. The MI-OTA and the filter circuits were designed and simulated in Cadence/Spectre environment using 0.18 µm CMOS process from TSMC. The simulation results agree well with theory and confirm the filter functionality.

A 0.25-V Rail-to-Rail Three-Stage OTA With an Enhanced DC Gain

This brief proposes a 0.25V rail-to-rail three stage OTA. The proposed OTA improves a DC gain by inserting an NMOS gate-driven amplifier into the conventional bulk-driven OTA. In addition, it uses an asymmetric self-cascode transistor and an indirect feedback compensation to enhance a DC gain and an unit-gain frequency. At the first stage, the bulk-driven amplifier has a rail-to-rail input, but it has a low DC gain due to a small transconductance. At the second stage, the NMOS gate-driven amplifier enhances the DC gain. At the last stage, the common-source amplifier drives an output load capacitor. The proposed OTA was fabricated using a 65nm CMOS process. Its area is 0.002mm2. It consumes $0.026~\mu \text{W}$ at the supply-voltage of 0.25V. The DC gain and unit-gain frequency are 70dB and 9.5kHz, respectively, with the phase margin of 88° at the load capacitance of 15pF.

Single-stage multipath class-AB bulk-driven OTA with enhanced power efficiency

A single-stage multipath class-AB bulk-driven operational transconductance amplifier working in weak inversion region with enhanced power efficiency is presented in this paper. The proposed bulk-driven amplifier makes use of four signal path to conduct small signal current, which leads to significant enhancement of transconductance when compared to conventional recycling structure. In addition, two of the signal paths build output stage operating at class-AB, resulting in a boost of slew rate. Most of all, the power efficiency of the proposed amplifier is improved over that of traditional recycling counterpart, enabling it more suitable for low-power applications. Simulated on SMIC 180 nm process, results demonstrate that the proposed bulk-driven amplifier achieves a 256% slew rate improvement and 100% unity-gain bandwidth enhancement when compared to the conventional recycling structure.

A hybrid-mode bulk-driven folded cascode OTA with enhanced unity-gain bandwidth and slew rate

A hybrid-mode bulk-driven folded cascode OTA with the enhanced unity-gain bandwidth and slew rate is presented in this paper. To achieve a faster large-signal transient response, a hybrid-mode output stage composed of a traditional folded cascode and an additional current mirror output stage is proposed. The proposed hybrid-mode output stage activates the additional current mirror output stage to produce a large transient charge/discharge current when slewing happens, overcoming the issue of limitation of folded current source in traditional folded cascode structure. By the combination of super bulk-driven input stage and proposed hybrid-mode output stage, not only does the bulk-driven folded cascode OTA achieve a large unity-gain bandwidth and high dc gain, but also the large-signal transient response is significantly improved. Designed under SMIC 0.18 μm process, simulation results demonstrate that the proposed bulk-driven OTA achieves 2 times the unity-gain bandwidth and 12 times the slew rate of conventional counterpart at the same power dissipation.

An approach to essentially improve current efficiency for bulk-driven OTA

An approach to essentially improve the current efficiency for the bulk-driven circuits is presented. By employing an auxiliary amplifier cross-coupled to the gate of bulk-driven flipped voltage follower and input differential pairs, it achieves not only the gain-bandwidth improved, but also the slew rate significantly enhanced, which leads to a great boost in current efficiency. To validate our introduced method, the conventional and the proposed bulk-driven amplifiers are both designed under the CSMC 0.18 μm technology. Simulation results demonstrate that bulk-driven amplifier based on the proposed method achieves an 8 times slew rate and a 4 times bandwidth improvement with only a negligible increase in power consumption.

A 0.25-V 22-nS symmetrical bulk-driven OTA for low-frequency $$G_m$$ G m -C applications in 130-nm digital CMOS process

This paper presents a 0.25-V supplied bulk-driven symmetrical OTA implemented in 130-nm CMOS process. By operating in weak inversion, and using a distributed layout approach, the OTA can benefit from the voltage reduction and high linearity enabled by halo-implanted transistors. The proposed circuit consumes only 10-nW, features a low transconductance of 22-nS, and a total harmonic distortion of 0.53 % for a 100-mVpp input voltage, thus making it suitable for low-frequency and low-power $$G_m$$ G m -C applications.