Buffer-related Current Collapse Research Articles

The Influence of Fe Doping Tail in Unintentionally Doped GaN Layer on DC and RF Performance of AlGaN/GaN HEMTs

In this work, the performance of AlGaN/ gallium nitride (GaN) high-electron mobility transistors (HEMTs) with different Fe doping tails was systematically investigated and compared. It is illustrated that the combination of the unintentionally doped (UID) GaN layer and a thinner Fe doping buffer layer would result in a faster slope rate of Fe concentration in the UID GaN layer. The devices with the fastest slope rate of Fe concentration in the UID GaN layer exhibited excellent large signal performance, including the saturated power density ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${P}_{sat}$ </tex-math></inline-formula> ) of 9 W/mm and the power-added efficiency (PAE) of 65.6%. In addition, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${P}_{sat}$ </tex-math></inline-formula> and the PAE of the device with the fastest slope rate of Fe concentration in UID GaN layer are 27.7% and 14.7%, which are higher than that of the device with the slowest slope rate of Fe concentration under the class AB operation conditions. Pulse <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}$ </tex-math></inline-formula> ,– <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> measurement results demonstrated that the buffer-related current collapse was more effectively suppressed in the 0.5- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> Fe doping buffer layer because of faster slope rate of Fe concentration in UID GaN layer. Moreover, the frequency-dependent capacitance and conductance measurement results indicated that the current collapse was relevant to deep traps in the UID GaN layer introduced by Fe doping. By reducing the concentration of the deep traps caused by Fe doping, the device showed excellent characteristics of dc and RF. Furthermore, controlling the Fe doping tail was important for designing the GaN-based power amplifier with high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${P}_{sat}$ </tex-math></inline-formula> and PAE.

Insight into Buffer Trap-Induced Current Saturation and Current Collapse in GaN RF Heterojunction Field-Effect Transistors

Buffer traps in GaN RF heterostructure field-effect transistors (HFETs) provide a high dc output resistance on one hand but induce the current collapse effect on the other hand. Here, we show that traps do not merely confine the carriers into the channel, but serve to pin the Fermi level. Only by pinning the Fermi level a high saturated dc output resistance can be obtained in short channel devices. If carriers are confined into the channel by a back-barrier, and no traps are present, then short channel effects still severely reduce the saturated dc output resistance. In addition, we show that the buffer-related current collapse, which manifests as an output conductance under RF or pulse conditions, can straightforwardly be explained by a simple capacitive coupling model between the drain and the channel under the gate. The trapped charge under the gate results in a pulse voltage step-dependent shift in threshold voltage. Based on this picture, current collapse at pulsed condition can be approximately evaluated from dc simulations or from capacitance measurements.

Characterization of Buffer-Related Current Collapse by Buffer Potential Simulation in AlGaN/GaN HEMTs

In this paper, the buffer-related current collapse (CC) in AlGaN/GaN HEMTs is investigated by using pulsed I–V measurements and 2-D drift-diffusion simulations. The simulation results indicate that the negative potential (NP), appearing in the Fe-doped buffer under the gate, is found to account for the CC. The NP will induce threshold voltage shifts, in which an inflection point (IP) of the threshold voltage is found. It could be revealed in pulsed I–V characteristics which are significant to depict trapping effect when building a compact large-signal model. The formation mechanism of the IP is detailed. In the end, a simple threshold voltage model is proposed for verification.

Impact of Substrate Bias Polarity on Buffer-Related Current Collapse in AlGaN/GaN-on-Si Power Devices

Bulk traps in the high-resistivity buffer stack underneath the 2-dimensional electron gas (2DEG), which can interact with the high vertical electric field at OFF state, impose a critical challenge to the dynamic ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}})$ of AlGaN/GaN-on-Si power devices. In this paper, the impact of substrate bias polarity on carrier injection/transport and buffer-induced current collapse has been investigated by using ramped and transient back-gating characterizations as well as TCAD simulations. High voltage applied to the conductive Si substrate can modulate 2DEG conductivity through the back-gate effect, whereby the dynamics of both acceptor and donor buffer traps are identified. Distinct buffer trapping and asymmetric vertical leakage under opposite top-to-substrate bias polarities have been observed, which are attributed to the fundamentally different carrier injection/transport mechanisms. It is suggested that the energy barrier at the nucleation-layer/Si interface can limit the electron injection from Si substrate into the buffer stack and consequently influence the buffer-related current collapse.

Control of Buffer-Induced Current Collapse in AlGaN/GaN HEMTs Using SiNx Deposition

The stoichiometry of low-pressure chemical vapor deposition SiN x surface passivation is shown to change vertical conductivity at the top of the epitaxial stack in GaN-on-Si power high-electron mobility transistors (HEMTs). This changes the charge stored in the carbon-doped GaN layer during high-voltage operation, and allows direct control of buffer-related current collapse in HEMTs. Substrate bias ramps are used to identify the changes in C:GaN charge trapping and vertical leakage. Channel length dependence indicates a lateral conductivity in the C:GaN with a localized increase in vertical conductivity under the ohmic contacts. An optimum SiN x recipe is identified which simultaneously delivers low current collapse and low drain leakage.

Investigation of Surface- and Buffer-Induced Current Collapse in GaN High-Electron Mobility Transistors Using a Soft Switched Pulsed \(I-V\) Measurement

In this letter, we investigated the behaviors of surface- and buffer-induced current collapse in AlGaN/GaN high-electron mobility transistors (HEMTs) using a soft-switched pulsed \(I-V\) measurement with different quiescent bias points. It is found that the surface- and buffer-related current collapse have different relationship with the gate and drain biases ( V \(_{\mathrm { {\!GS0,}}}\) V \(_{\mathrm { {\!DS0}}}\) ) during quiescent bias stress. The surface-induced current collapse in devices without passivation monotonically increases with the negative V \(_{\mathrm { {\!GS0}}}\) , suggesting that an electron injection to the surface from gate leakage is the dominant mechanism and the Si3N4 passivation could effectively eliminate such current collapse. The buffer-induced current collapse in devices with intentionally carbon-doped buffer layer exhibits a different relationship with V \(_{\mathrm { {\!GS0}}}\) after surface passivation. The buffer-related current collapse shows a bell-shaped behavior with V \(_{\mathrm { {\!GS0}}}\) , suggesting that a hot electron trapping in the buffer is the dominant mechanism. The soft-switched pulsed \(I-V\) measurement provides an effective method to distinguish between the surface- and buffer-related current collapse in group III-nitride HEMTs.

Effect of GaN Channel Layer Thickness on DC and RF Performance of GaN HEMTs With Composite AlGaN/GaN Buffer

The effects of GaN channel layer thickness on dc and RF performance of AlGaN/GaN high-electron mobility transistors (HEMTs) with a state-of-the-art composite AlGaN/GaN (1/1 μm) buffer were systematically investigated. Although HEMTs with a thick GaN channel layer exhibit slight degraded dc and RF small-signal performance associated with short-channel effects, they demonstrate significantly enhanced OFF-state breakdown voltage and RF large-signal performance. The 1-mm HEMTs with a 150-nm-thick GaN channel layer feature a 1.4 dB higher saturated POUT and about 10% higher PAE than that with a 50-nm-thick GaN channel layer, in both Classes AB and B operation conditions. Pulse I-V characterization reveals that the buffer-related current collapse is also suppressed in the thick GaN channel sample as compared with the thin one, suggesting that a thick GaN channel layer will not only reduces the deep traps in the channel, but also reduces the electron capture probability by deep traps in the composite AlGaN/GaN buffer. The selection of a proper GaN channel layer thickness is thus of great importance to the designation of GaN-based power amplifiers for various applications.

Analysis of Lags and Current Collapse in Source-Field-Plate AlGaN/GaN High-Electron-Mobility Transistors

A two-dimensional transient analysis of source-field-plate AlGaN/GaN high-electron-mobility transistors (HEMTs) is performed by considering a deep donor and a deep acceptor in a buffer layer, and the results are compared with those in the case of gate-field-plate structures. It is shown that the reduction rate of drain lag obtained by introducing a field plate is quantitatively similar between source- and gate-field-plate structures. However, the gate-lag rate is rather higher in the source-field-plate structure because the electric field at the drain edge of the gate is higher in the off state, and hence electron injection into the buffer layer and the resulting trapping effects are more significant. Hence, current collapse is slightly larger in the source-field-plate structure. It is also shown that an optimum SiN passivation layer thickness is required to minimize buffer-related current collapse in source-field-plate AlGaN/GaN HEMTs.

Analysis of backside-electrode and gate-field-plate effects on buffer-related current collapse in AlGaN/GaN high electron mobility transistors

Two-dimensional transient analysis of gate-field-plate AlGaN/GaN high electron mobility transistors with a backside electrode is performed by considering a deep donor and a deep acceptor in a buffer layer. Effects of introducing a field plate and a backside electrode on buffer-related lag and current collapse are studied. It is shown that gate field plate introduction is effective in reducing lag and current collapse when the acceptor density in the buffer layer is high. On the other hand, backside electrode introduction is shown to be effective in reducing drain lag and current collapse, particularly when the acceptor density in the buffer layer is relatively low, because the fixed potential at the backside electrode reduces electron injection into the buffer layer and the resulting trapping effects.

Analysis of field-plate effects on buffer-related lag phenomena and current collapse in GaN MESFETs and AlGaN/GaN HEMTs

A two-dimensional transient analysis of field-plate GaN MESFETs and AlGaN/GaN HEMTs is performed in which a deep donor and a deep acceptor are considered in a semi-insulating buffer layer, and quasi-pulsed current–voltage curves are derived from them. How the existence of a field plate affects buffer-related drain lag, gate lag and current collapse is studied. It is shown that in both MESFET and HEMT, the drain lag is reduced by introducing a field plate because electron injection into the buffer layer is weakened by it, and the buffer-trapping effects are reduced. It is also shown that the field plate could reduce buffer-related current collapse and gate lag in the FETs. The dependence of lag phenomena and current collapse on the field-plate length and on the SiN passivation layer thickness is also studied. The work suggests that in the field-plate structures, there is an optimum thickness of the SiN layer to minimize the buffer-related current collapse and drain lag in GaN MESFETs and AlGaN/GaN HEMTs.