Buffer Planning Research Articles

Combining Simulation and Optimisation to Design Reliable Transportation Services with Autonomous Fleets

We develop and investigate reliable services for autonomous freight and passenger transport in urban areas. We consider the individual requirements of travelers for reliable arrival times. To ensure these in an environment of congested urban traffic networks, we investigate how much buffer we need while avoiding excessive idle times. Using the traffic simulation MATSim, we derive time-dependent travel times, integrate them into offline buffer planning, and evaluate the resulting tours. We implement and compare the use of standard deviation and an adapted linear programming model to define buffers and to enable more reliable transportation services at affordable costs.

Mathematical Model for Proactive Resequencing of Mixed Model Assembly Lines

Abstract Mixed model assembly lines are state of the art for automotive mass production. In the context of mass customization and indi-vidualization the car sequencing recently became more and more challenging due to varying assembly tasks and processing times. Classical principles such as the vehicle pearl chain are thus reaching their limits. Therefore, planned changes in the vehicle sequence during final assembly, Proactive Resequencing, was proposed to optimize utilization segment by segment. The concept leads to a long-term buffer planning problem on a strategic level as well as to an adapted vehicle sequencing problem with enhanced flexibility on an operative level. This paper introduces a mathematical model for the combined buffer planning and order sequencing problem for automotive assembly lines. It also outlines a solution approach for the mentioned production planning challenges separated by their timing preferences.

Buffer Planning for IP Placement Using Sliced-LFF

IP cores are widely used in modern SOC designs. Hierarchical design has been employed for the growing design complexity, which stimulates the need for fixed-outline floorplanning. Meanwhile, buffer insertion is usually adopted to meet the timing requirement. In this paper, buffer insertion is considered with a fixed-outline constraint using Less Flexibility First (LFF) algorithm. Compared with Simulated Annealing (SA), our work is able to distinguish geometric differences between two floorplan candidates, even if they have the same topological structure. This is helpful to get a better result for buffer planning since buffer insertion is quite sensitive to a geometric change. We also extend the previous LFF to a more robust version called Sliced-LFF to improve buffer planning. Moreover, a 2-staged LFF framework and a post-greedy procedure are introduced based on our net-classing strategy and finally achieve a significant improvement on the success rate of buffer insertion (40.7% and 37.1% in different feature sizes). Moreover, our work is much faster than SA, since it is deterministic without iterations.

Handling routability in floorplan design with twin binary trees

As technology moves into the deep-submicron era, the complexities of VLSI circuits grow rapidly. Interconnect optimization has become an important concern. Most routability-driven floorplanners [H.M. Chen, H. Zhou, F.Y. Young, D.F. Wong, H.H. Yang, N. Sherwani, Integrated floorplanning and interconnect planning, in: Proceedings of IEEE International Conference on Computer-Aided Design, 1999, pp. 354–357; S. Krishnamoorthy, J. Lou, H.S. Sheng, Estimating routing congestion using probabilistic analysis, in: Proceedings of International Symposium on Physical Design, 2001, pp. 112–117; M. Wang, M. Sarrafzadeh, Modeling and minimization of routing congestion, in: IEEE Asia and South Pacific Design Automation Conference, 2000, pp. 185–190] use grid-based approach that divides a floorplan into grids as in global routing to estimate congestion by the expected number of nets passing through each grid. This approach is direct and accurate, but not efficient enough when dealing with complex circuits containing many nets. In this paper, an efficient and innovative interconnect-driven floorplanner using twin binary trees (TBT) representation [B. Yao, H. Chen, C.K. Cheng, R. Graham, Revisiting floorplan representations, in: Proceedings of International Symposium on Physical Design, 2001, pp. 138–143; E.F.Y. Young, C.C.N. Chu, Z.C. Shen, Twin binary sequences: a non-redundant representation for general non-slicing floorplan, in: Proceedings of International Symposium on Physical Design, 2002, pp. 196–201] is proposed. The estimations are based on the wire densities (number of wires passing through per unit length) on the half-perimeter boundaries of different regions in a floorplan. These regions are defined naturally by the TBT representation. Buffer planning is also considered by deciding if buffers can be inserted successfully for each net. In order to increase the efficiency of our floorplanner, a fast algorithm for the least common ancestor (LCA) problem in Bender and Farach-Colton [The LCA problem revisited, in: Latin American Theoretical INformatics, 2000, pp. 88–94] is used to compute wire density, and a table look-up approach is used to obtain the buffer insertion information. Experimental results show that our floorplanner can reduce the number of unroutable wires. The performance is comparable with other interconnect-driven floorplanners that perform global routing-like operations directly to estimate routability, but our estimation method is much faster and is scalable for large complex circuits.

Buffer planning for application-specific networks-on-chip design

Networks-on-chip (NoC) is a promising communication architecture for next generation SoC. The size of buffer used in on-chip routers impacts the silicon area and power consumption of NoC dominantly. It is important to plan the total buffer-size and each router buffer-allocation carefully for an efficient NoC design. In this paper, we propose two buffer planning algorithms for application-specific NoC design. More precisely, given the traffic parameters and performance constraints of target application, the proposed algorithms automatically determine minimal buffer budget and assign the buffer depth for each input channel in different routers. The experimental results show that the proposed algorithms can significantly reduce total buffer usage and guarantee the performance requirements.

Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing

As VLSI technologies scale down, interconnect performance is greatly affected by crosstalk noise due to the decreasing wire separation and increased wire aspect ratio, and crosstalk has become a major bottleneck for design closure. The effectiveness of traditional buffering and spacing techniques for noise reduction is constrained by the limited available resources on chip. In this paper, we present a method for incorporating crosstalk reduction criteria into global routing under a broad power supply network paradigm. This method utilizes power/ground wires as shields between signal wires to reduce capacitive coupling, while considering the constraints imposed by limited routing and buffering resources. An iterative procedure is employed to route signal wires, assign supply shields, and insert buffers so that both buffer/routing capacity and signal integrity goals are met. In each iteration, shield assignment and buffer insertion are considered simultaneously via a dynamic programming-like approach. Our noise calculations are based on Devgan's metric, and our work demonstrates, for the first time, that this metric shows good fidelity on average. An effective noise margin inflation technique is also proposed to compensate for the pessimism of Devgan's metric. Experimental results on testcases with up to about 10000 nets point towards an asymptotic runtime that increases linearly with the number of nets. Our algorithm achieves noise reduction improvements of up to 53% and 28%, respectively, compared to methods considering only buffer insertion or only shield insertion after buffer planning.

An algorithm for integrated pin assignment and buffer planning

The buffer block methodology has become increasingly popular as more and more buffers are needed in deep-submicron design, and it leads to many challenging problems in physical design. In this article, we present a polynomial-time exact algorithm for integrated pin assignment and buffer planning for all two-pin nets from one macro block (source block) to all other blocks of a given buffer block plan, while minimizing the total cost α ˙ W + β ˙ R for any positive α and β where W is the total wirelength, and R is the number of buffers. By applying this algorithm iteratively (each time, pick one block as the source block), it provides a polynomial-time algorithm for pin assignment and buffer planning for nets among multiple macro blocks. Experimental results demonstrate its efficiency and effectiveness.

Buffer planning as an Integral part of floorplanning with consideration of routing congestion

The dominating contribution of interconnect to system performance has made it critical to plan the resources of the buffers and routes in the early stage of the layout. In this paper, we integrate floorplanning with buffer insertion for performance-driven design processes. We devise a two-step method to evaluate the feasible buffer insertion sites, which can improve the efficiency of the buffer-planning algorithm. By partitioning all empty spaces into blocks in the packing process, the buffer allocation is handled as an integral part of the floorplanning. Our buffer-planning algorithm maps the buffers into tiles with consideration of routing congestion. In this approach, we construct a distribution graph to model the possible routes. The buffer allocation method is performed on the updated distribution graph to find the buffer locations with their respective congestion costs. The method is based on a simulated annealing approach, which is composed of multiple phases to speed up the optimization. Since there is more freedom with floorplan optimization, the empirical results demonstrate better performance.

A generic-traffic optical buffer modeling for asynchronous optical switching networks

Delay-line buffering has emerged as the current time-domain contention; solution in optical switching networks. Due to the unpredictability of future Internet traffic and the existence of various buffer architectures and wavelength scheduling policies, the study of such buffers under different traffic conditions is a very important issue. In this paper we present a generic-traffic analytical model for the FIFO delay-line buffer in an asynchronous network scenario that may be useful for buffer planning and performance evaluation. The model is traffic generic as it may assume any inter-arrival time process and packet length distribution.

Routability-driven floorplanner with buffer block planning

In traditional floorplanners, area minimization is an important issue. However, due to the recent advances in very large scale integration technology, the number of transistors in a design are increasing rapidly and so are their switching speeds. This has increased the importance of interconnect delay and routability in the overall performance of a circuit. We should consider interconnect planning, buffer planning, and routability as early as possible. In this paper, we study and implement a routability-driven floorplanner with congestion estimation and buffer planning. Our method is based on a simulated annealing approach that is divided into two phases: the area optimization and congestion optimization phases. In the area optimization phase, modules are roughly placed according to the total area and wirelength. In the congestion optimization phase, a floorplan is evaluated by its area, wirelength, congestion, and routability. We assume that buffers should be inserted at flexible intervals from each other for long enough wires and probabilistic analysis is performed to compute the congestion information taken into account the constraints in buffer locations. Our approach is able to reduce the average number of wires at the congested areas and allow more feasible insertions of buffers to satisfy the delay constraints without having much penalty in increasing the area of the floorplan.

Maze routing with buffer insertion and wiresizing

The authors propose an elegant formulation of the Maze Routing with Buffer Insertion and Wiresizing problem as a graph-theoretic shortest path problem. This formulation provides time and space performance improvements over previously proposed dynamic programming based techniques. Routing constraints such as wiring obstacles and restrictions on buffer locations and types are easily incorporated in the formulation. They construct a buffer planning (BP)-graph such that the length of every path in this graph is equal to the Elmore delay. Therefore, finding the minimum Elmore delay path becomes a finite shortest path problem. The buffer choices and insertion locations are represented as the vertices in the BP-graph. The interconnect wires are sized by constructing a look-up table for buffer-to-buffer wiresizing solutions. The authors also provide a technique that is able to tremendously improve the runtime. Experiments show improvements over previously proposed methods.

Network flow based buffer planning

The problem of planning the locations of large number of buffers is of utmost importance in deep submicron VLSI design. Recently, [Cong, Kong, and Pan ICCAD-99, 1999, p. 358] proposed an algorithm to directly address this problem. Given a placement of circuit blocks, a key step in [1] is to use the free space between the circuit blocks for inserting as many buffers as possible. This step is very important because if all buffers can be inserted into existing spaces, no expansion of chip area would be needed. An effective greedy heuristic was used in [1] for this step. In this paper, we give a polynomial-time optimal algorithm for solving the problem of inserting maximum number of buffers into the free space between the circuit blocks. In the case where the “costs” of placing a buffer at different locations are different, we can guarantee to insert maximum number of buffers with minimum total cost. Our algorithm is based on efficient min-cost network-flow computations.