Bridging Grains Research Articles

Reversely-Synchronized-Stress-Induced Degradation in Polycrystalline Silicon Thin-Film Transistors and Its Suppression by a Bridged-Grain Structure

In this letter, a reversely synchronized stress (RSS) is proposed to simulate the working condition of switching thin-film transistors (TFTs) in active-matrix displays. The reliability of polycrystalline silicon (poly-Si) TFTs under RSS is characterized and investigated. RSS brings huge device degradation. A dynamic hot carrier (HC) effect, dependent on transition edges of RSS, dominates the degradation. Combined with a transient simulation, the degradation mechanism under RSS in poly-Si TFTs is discussed and developed. To suppress RSS-induced HC degradation, a bridged-grain (BG) structure is employed in the active layer of poly-Si TFTs. Via BG lines’ reducing the lateral electric field in the channel at source/drain sides, the reliability of BG TFTs under RSS is significantly improved.

High‐Performance Polycrystalline Silicon Thin‐Film Transistors without Source/Drain Doping by Utilizing Anisotropic Conductivity of Bridged‐Grain Lines

AbstractBy utilizing anisotropic conductivity of bridged‐grain (BG) lines, a polycrystalline silicon (poly‐Si) thin‐film transistor (TFT) without source/drain (S/D) doping is designed, simulated, and fabricated. In the new design, the current is made to flow along the BG lines in the S/D region and flow perpendicularly to the BG lines in the channel. By taking advantage of the anisotropic conductivity of the BG lines, the S/D doping process is eliminated and the fabrication process cost is reduced. Meanwhile, the advantages of adopting BG lines are maintained. The as‐fabricated TFTs without S/D doping exhibit excellent device characteristics, compared with normal TFTs. The reliability of TFTs without S/D doping is also evaluated under hot carrier stress and negative/positive bias stress. Additionally, the proposed new TFT structure allows a wider range of dopant activation conditions.

P‐6.6: Effects of lightly Doped Drain Structure in n‐channel ELA Bridged‐Grain Poly‐Si TFTs

We lead the lightly doped drain (LDD) structure into the bridged‐grain (BG) poly‐Si thin film transistor (TFT). This combined structure can restrain the gate induced drain leakage current (GIDL) and the electrical characteristics shows not much sacrifice. A high Ion/Ioff current ratio 3.79×108 is achieved. Besides, the device reliability is improved significantly. Because the lateral electrical field decreases by LDD, lower trap state density is generated in the SiO2/poly‐Si interface and the grain boundaries of poly‐Si near the surface conduction channel, resulting in the stable on‐state drive current (Ion) and drain saturation voltage (Vdsat). All test results indicate that the BG poly‐Si TFT with a LDD structure will work well and has a great potential for system‐on‐panel application.

“Driving”-Stress-Induced Degradation in Polycrystalline Silicon Thin-Film Transistors and Its Suppression by a Bridged-Grain Structure

In this letter, degradation of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) under “driving” stress is characterized and analyzed for the first time. Dynamic hot carrier (HC) effect, related to pulse falling time, dominates device degradation. To suppress such “driving”-stress-induced dynamic HC degradation, a bridged-grain (BG) structure is applied to the active channel of poly-Si TFTs. Due to the lateral electric field reduction at source/drain junctions, “driving”-stress-induced dynamic HC degradation is significantly improved by the BG structure. Incorporated with transient simulations, the degradation mechanism is elucidated.

Dynamic-Gate-Stress-Induced Degradation in Bridged-Grain Polycrystalline Silicon Thin-Film Transistors

In this paper, degradation behaviors of bridged-grain (BG) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) are systematically characterized and investigated. Device degradation exhibits a two-stage behavior, which is related to pulse falling time ( $t_{f}$ ). A faster $t_{f}$ brings a larger ON-current ( $I_{\mathrm{\scriptscriptstyle ON}}$ ) increase in the first stage and a larger $I_{\mathrm{\scriptscriptstyle ON}}$ decrease in the second stage. Electron trapping/injection into gate oxide and dynamic hot carrier effect are found to be responsible to $I_{\mathrm{\scriptscriptstyle ON}}$ increase in the first stage and $I_{\mathrm{\scriptscriptstyle ON}}$ decrease in the second stage, respectively. Compared with normal poly-Si TFTs, BG poly-Si TFTs show much more reliable performance under the same dynamic gate stress. The larger $I_{\mathrm{\scriptscriptstyle ON}}$ increase in the first stage in BG poly-Si TFTs is attributed to the enhanced vertical electric field in the channel near the gate oxide, while the much smaller $I_{\mathrm{\scriptscriptstyle ON}}$ decrease in the second stage is attributed to lateral electric field reduction caused by the sharing of the field across multiple reversely biased junctions inside the active channel. Incorporated with transient simulations, the degradation mechanisms for both the first stage and the second stage are elucidated. In addition, the impact of the first-stage degradation on the second-stage degradation is also clarified.

Fabrication of High-Performance Bridged-Grain Polycrystalline Silicon TFTs by Laser Interference Lithography

In this paper, bridged-grain (BG) low-temperature polycrystalline silicon thin-film transistors (TFTs) were fabricated. The periodic submicrometer BG structures were patterned using a maskless and large-area applicable laser interference lithography (LIL) technology, which was able to minimize extra manufacture costs of BG structures. Compared with conventional metal-induced crystallized (MIC) poly-Si TFTs, the BG-MIC TFTs involving the LIL technology exhibited reduced threshold voltage and subthreshold swing, improved ON–OFF current ratio, and suppressed leakage current and kink effect. Since the exposure energy density is one of key parameters for LIL, its relationship with device electrical performance was further investigated. It was found that when the exposure energy density was in the vicinity of 60 mJ/cm2, these BG-MIC TFTs could perform optimally without device uniformity degradation.

P‐24: Optimization of the Fabrication Process for Bridged‐Grain Metal Induced Crystallization TFTs

Bridged‐grain (BG) metal induced crystallization (MIC) thin film transistor (TFTs) technology has great potential to realize next generation high resolution and large size flat‐panel displays. The required time for MIC crystallization process of amorphous silicon (a‐Si) thin film is typically about 10 hours in inert atmosphere. In this paper we proposed two optimized schemes for BG‐MIC TFTs to improve the device performance and reduce the process time.

Significant Reduction of Dynamic Negative Bias Stress-Induced Degradation in Bridged-Grain Poly-Si TFTs

The device degradation of bridged-grain (BG) polycrystalline silicon thin-film transistors under dynamic negative bias stress (NBS) is investigated for the first time. By employing a BG structure in the active channel, dynamic NBS-induced hot carrier degradation could be significantly reduced from -99.9% to -2.4% (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> s dynamic NBS), which is attributed to a sharing of the lateral electric field across the multiple p-n junctions inherent in the structure. The nonequilibrium junction degradation model is employed and developed, incorporated with TCAD simulations.

搭桥晶粒多晶硅薄膜晶体管直流电应力下的退化行为与退化机制研究

Degradation behaviors and degradation mechanisms of bridged-grain(BG)polycrystalline silicon thin film transistors(TFTs)under DC bias stresses are studied and investigated.Compared to normal poly-Si TFTs,BG poly-Si TFTs exhibits better negative bias temperature instability(NBTI),better self-heating(SH)reliability and better hot carrier(HC)reliability.All these DC reliability improvements come from BG lines inside the active channel.By selectively doping the active channel in BG poly-Si TFTs,boron-hydrogen bonds formation at oxide/channel interface and grain boundaries,Joule heat diffusion enhancement at channel length direction and lateral electric field reduction at the drain side are respectively responsible for the improved NBTI reliability,SH reliability and HC reliability.All test results indicate that such high performance and high reliable BG poly-Si TFTs havegreat potential in system-on-panel applications.

Characterization of DC-Stress-Induced Degradation in Bridged-Grain Polycrystalline Silicon Thin-Film Transistors

In this paper, dc-stress-induced degradation in bridged-grain (BG) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) is systemically characterized and investigated. Compared with normal poly-Si TFTs, BG poly-Si TFTs exhibit better hot-carrier (HC) reliability, better self-heating (SH) reliability, and better negative bias temperature (NBT) instability. Resulting from the heavily doped BG lines inside the active channel, lateral electric field reduction at the drain side, Joule heat diffusion enhancement at the channel length direction, and boron-hydrogen bond formation at interface/grain boundaries are, respectively, responsible for the improved HC reliability, SH reliability, and NBT reliability in BG poly-Si TFTs. In addition, stress V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> -dependent HC degradation with fixed stress Vd, stress power density-dependent SH degradation, and vertical electrical field-dependent NBT degradation are also examined in both normal poly-Si TFTs and BG poly-Si TFTs. All test results indicate that such high-performance and highly reliable BG poly-Si TFT has a great potential for system-on-panel application.

P‐6: Static Reliability of Bridged‐Grain Poly‐Si TFTs

AbstractThe characteristics of bridged‐grain (BG) poly‐Si thin film transistors (TFTs) with different BG periods and the static reliability of BG poly‐Si TFTs was examined and discussed. The characterizations show that the length of the sub‐channels mainly affects the on‐state current and the sub‐threshold characteristics. BG TFTs exhibit better hot carrier reliability, better self‐heating reliability, better negative bias temperature instability and good immunity against water.

Study of the Characteristics of Solid Phase Crystallized Bridged-Grain Poly-Si TFTs

In this paper, bridged-grain (BG) poly-Si thin-film transistors (TFTs) were fabricated. The characteristics of BG poly-Si TFTs with different BG periods and implantation schemes were investigated. The poly-Si TFTs with optimized BG structures and doping schemes demonstrated greatly improved sub-threshold slope, threshold voltage, maximum field effect mobility, leakage current, and ON/OFF ratio.

Bridged-Grain Solid-Phase-Crystallized Polycrystalline-Silicon Thin-Film Transistors

Novel bridged-grain (BG) technique is applied in the fabrication of low-temperature solid-phase-crystallized polycrystalline-silicon thin-film transistors. As a result of improved current flow and reduction of high drain electric field, the subthreshold slope, threshold voltage, maximum field-effect mobility, leakage current, and on-off ratio are greatly improved. Mechanisms of BG conduction are studied in detail.

P‐9: Bridged Grain MIC Poly‐Si Thin‐Film Transistors with Sputtered AlOx as Gate Dielectrics

AbstractBridged grain (BG) technology was applied to fabricate MIC poly‐Si TFTs with AlOx gate dielectrics. The threshold voltage (Vth) and subthreshold swing (SS) of MIC TFTs are greatly improved. Meanwhile, the drawback of using high‐k dielectrics, such as large off‐state leakage current and early kink effect was effectively suppressed by using BG structure. Combination of BG and high‐k gate insulators makes the resulting device a promising candidate for system on panel applications.

(Invited) Bridged-grain (BG) Polycrystalline Silicon Thin Film Transistors (TFTs)

A new technique bridged-grain (BG) was introduced. Using this BG excimer laser annealing (ELA) poly-Si as an active layer, the grain boundary effects can be minimized. Important electrical properties such as sub-threshold swing, threshold voltage, maximum field effect mobility, leakage current, on-off ratio and device uniformity across the substrate can all be improved using the present technique. The improvement can be achieved at low cost, thus making inexpensive, high performance LTPS TFT a reality.

59.3: Bridged‐grain (BG) Eximer Laser Annealing (ELA) Polycrystalline Silicon Thin Film Transistors (TFTs)

AbstractA new technique bridged‐grain (BG) was introduced. Using this BG eximer laser annealing (ELA) poly‐Si as an active layer, the grain boundary effects can be reduced. Important electrical properties such as sub‐threshold swing, threshold voltage, maximum field effect mobility, leakage current, on‐off ratio and device uniformity across the substrate can all be improved using the present technique. The improvement can be achieved at low cost, thus making inexpensive, high performance LTPS TFT a reality.