Boundary Clock Research Articles

A Novel Algorithm for Establishing a Balanced Synchronization Hierarchy with Spare Masters (BSHSM) for the IEEE 1588 Precision Time Protocol

The best master clock (BMC) algorithm is currently used to establish the master-slave hierarchy for the IEEE 1588 Precision Time Protocol (PTP). However, the BMC algorithm may create an unbalanced hierarchy that contains several boundary clocks with a large number of slaves in comparison to other clocks. The unbalanced hierarchy can cause problems, such as high communication load and high bandwidth consumption in boundary clocks. Additionally, the BMC algorithm does not provide any fast recovery mechanism in the case of a master failure. In this paper, we propose a novel balanced synchronization hierarchy with spare masters (BSHSM) algorithm to establish a balanced master-slave hierarchy and to provide a fast recovery mechanism in the case of master failures for the PTP. The BSHSM algorithm establishes the master-slave hierarchy with boundary clocks that have a balanced number of slaves. In doing so, it solves the problems caused by the unbalanced master-slave hierarchy. Additionally, the BSHSM algorithm provides a fast recovery mechanism by selecting a spare master for each boundary clock; this allows a boundary clock to immediately select a new master clock when its current master has failed or is disconnected. The fast recovery mechanism reduces the period of running freely and clock drift in clocks, improving the synchronization quality of the PTP. Various simulations were conducted using the network simulation OMNeT++ v4.6 to analyze, evaluate, and compare the performance of the BSHSM and BMC algorithms. The simulation results show that the synchronization hierarchy of the BSHSM algorithm is much more balanced than the BMC algorithm, and it also has a shorter period of recovery.

Ethernet transport system supporting delay‐sensitive real‐time traffics

SUMMARYWe propose and demonstrate an Ethernet transport system that can support hard real‐time traffics with guaranteed throughput and very low jitter performance even in the presence of asynchronous traffics. The superframe structure‐based Ethernet system first synchronizes all the nodes in a network by using the IEEE 1588‐compliant boundary clock scheme and then reserves the traffic channels for synchronous traffics before accommodating both synchronous and asynchronous traffics in the superframe. Our experimental demonstration performed on field‐programmable gate array‐enabled Gigabit Ethernet test benches shows that the proposed scheme not only guarantees the throughput of the synchronous frames but also substantially reduces the jitter of the synchronous frames less than 110 ns after seven‐hop transmission. Copyright © 2013 John Wiley & Sons, Ltd.

On the Seamless Interconnection of IEEE1588-Based Devices Using a PROFINET IO Infrastructure

Several types of industrial Real-Time Ethernet (RTE) networks could be present in the same plant. This work deals with the clock synchronization problems that arise when different RTE network infrastructures are interconnected. Specifically, this paper is focused on the exploitation of PROFINET IO Conformance Class C infrastructure for the interconnection of other industrial communication devices or measurement instruments that use IEEE1588 for clock synchronization. Actually, such devices (e.g., LXI instruments, EtherNet/IP devices, etc.) cannot be satisfactorily synchronized if directly connected to the PROFINET infrastructure, because of the large time errors (up to 100 μs). The solution proposed in this paper is an intelligent clock synchronization converter that has fewer limitations if compared with other systems, like boundary clocks. The basic idea is the creation of a “black-box” (a sort of remote bridging device) for the interconnection of IEEE1588 nodes through a PROFINET IO host plant, with zero-configuration on both systems. The proposed approach differs from boundary clock since its goal is to keep the PROFINET IO and the IEEE1588 synchronization domains separated, exploiting the possibility to tunnel the IEEE1588 time information through the PROFINET IO infrastructure with sufficient precision. In order to verify the practical feasibility of the proposed solution, LXI Class B instruments have been connected to the infrastructure of a real PROFINET IO network. The results show that the standard deviation of the synchronization accuracy is only 10 ns higher than the one measured in the case of a dedicated (separated) network for the LXI instruments.

A Novel Method for Providing Precise Time Synchronization in a Distributed Control System Using Boundary Clock

We propose and demonstrate a method to provide precise time synchronization in distributed control systems using a boundary clock scheme. The major drawback of the boundary clock scheme is the exponential accumulation of time synchronization error as the number of hops increases. To make the error accumulation linearly increase with the number of hops, we first separate the frequency compensation interval (FCI) and the offset and frequency compensation interval (OFCI) and then separately optimize each interval. To demonstrate the performance of this method, we implemented test benches using Ethernet-linked distributed control systems. We measured the peak-to-peak jitter performance along with the maximum time interval error to assess the short- and long-term stability after several hops in distributed control systems. Our method enables the peak-to-peak jitter to be maintained under 107 ns after seven hops. The experimental results show that the performance of time synchronization is dominated by fast jitter rather than frequency error and wander, and the proposed scheme can be used to improve the time synchronization performance in IEEE 1588-compliant control systems using boundary clock.

Onboard Digital Signal Processing Technologies for Present and Future TDMA Arid SCPC Systems

An appropriate sampling of devices and architectures for onboard TDMA (Time Division Multiple Access) equipment, burst modems, baseband switches, and SCPC (Single Channel per Carrier) multicarrier demodulators from the present to the year 2000 are selected and presented along with device technology development trends, in terms of minimizing onboard weight and power consumption. The results show that at the present time (equivalent to around the year 1990 for onboard use), onboard TDMA equipment with a clock rate of lower than 100 MHz can be reasonably realized by parallel-processed CMOS/BULK LSIC's, while for TDMA equipment with clock rates of higher than 100 MHz, bipolar devices are more appropriate. The boundary clock rate is not so rigid, and toward the year 2000, the boundary will move up to about 200 MHz. Moreover, around the year 2000, GaAs devices will be more widely used for onboard high-bit rate TDMA. It is shown that for carrier frequencies up to 2 GHz, modem implementation in monolithic microwave IC's is most suitable. Moreover, it is found that coherent demodulation will not entail a big penalty in hardware size and power consumption, because of implementing carrier recovery circuits using IC's and LSIC's. As potential baseband switch configurations, a single <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</tex> -stage and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T-S-T</tex> architecture are compared, and suitable throughputs and TDMA frame lengths for each architecture are clarified. For SCPC multicarrier demodulators, the selection of demodulation schemes depends on the number of channels available for regeneration onboard the satellite. Therefore, in this paper, for years 1990, 1995, and 2000, the total weight and power consumption for several suitable onboard multicarrier demodulation schemes are studied as a function of the number of channels to be regenerated.