Bordered Block Diagonal Research Articles

An Efficient Parallel Sequential Approach for Transient Stability Emergency Control of Large-Scale Power System

Generator-tripping and load-shedding are important emergency control measures to maintain the transient stability of the power system. In this paper, emergency control is modeled as a large-scale optimal control problem. An efficient parallel sequential approach, which consists of preprocessing layer, simulation layer, and optimization layer, is proposed to solve the problem. In the preprocessing layer, power system partitioning is performed to construct a Jacobian matrix of double-layered bordered block diagonal (BBD) structure, control variable selection and initialization are designed to reduce computation cost and improve convergence. In the simulation layer, the differential algebraic equations are solved in parallel with the sensitivity analysis by reusing the LU-factorizations. Based on the BBD structure of Jacobian matrix, a parallel block algorithm is proposed to further accelerate computation speed. In the optimization layer, the resulting nonlinear programming problem is efficiently solved by predictor–corrector interior point method. The efficiency and practicality of the proposed approach are verified by numerical experiments on three test systems.

Structure Detection in Mixed-Integer Programs

Despite vast improvements in computational power, many large-scale optimization problems involving integer variables remain difficult to solve. Certain classes, however, can be efficiently solved by exploiting special structure. One such structure is the singly bordered block-diagonal (BBD) structure that lends itself to Dantzig-Wolfe decomposition, Lagrangian relaxation, and branch and price. We start by introducing a new measure of goodness to capture desired features in BBD structures such as granularity of the structure, homogeneity of the block sizes, and isomorphism of the blocks. We then use it to propose a new approach to identify the best BBD structure inherent in the constraint matrix. The main building block of the proposed approach is the use of a community detection methodology in lieu of graph/hypergraph partitioning methods to alleviate one major drawback of the existing approaches in the literature: predefining the number of blocks. When tested on MIPLIB2003/2010 instances and compared against the state-of-the-art technique, the proposed algorithm is found to identify very good structures and require shorter CPU time to reach comparable bounds, in most cases.

A holistic fast and parallel approach for accurate transient simulations of analog circuits

The accurate analog simulation of critical circuit parts is a key task in the R&D process of integrated circuits. With the increasing complexity of integrated circuits it is becoming cumulatively challenging to simulate in the analog domain and within reasonable simulation time. Previous speedup approaches of the SPICE (Simulation Program with Integrated Circuit Emphasis) analog circuit simulator included either solver improvements and speedup or model order reduction of the semiconductor devices.In this paper we present a comprehensive approach to significantly speedup a SPICE-based analog circuit simulator while keeping the single-rate characteristic of time domain simulations. The novelty of our approach consists in the combination and extension of existing approaches in a unique way, enabling fast transient SPICE-level simulations. The main component of our approach is the circuit partitioner that combines relevant aspects from circuit theory and linear algebra in a unifying way. This enables the construction of an efficient and parallel BBD (bordered block diagonal) solver. Furthermore, this BBD structure allows for intrinsic model order reduction of the partitions during the Newton iteration, transforming the Newton method to a Quasi-Newton method.For mid-sized and large-sized circuits our BBD approach leads to significant sequential and parallel accelerations of transient simulations. Additional speedup can be gained from our block-bypass strategies exploiting the latency in the partitioned circuit. Altogether our approach leads to a speedup of up to two orders of magnitude compared to the state-of-the-art KLU solver while maintaining SPICE-level accuracy.

DC Large-Scale Simulation of Nonlinear Circuits on Parallel Processors

Abstract Newton-Raphson DC analysis of large-scale nonlinear circuits may be an extremely time consuming process even if sparse matrix techniques and bypassing of nonlinear models calculation are used. A slight decrease in the time required for this task may be enabled on multi-core, multithread computers if the calculation of the mathematical models for the nonlinear elements as well as the stamp management of the sparse matrix entries is managed through concurrent processes. In this paper it is shown how the numerical complexity of this problem (and thus its solution time) can be further reduced via the circuit decomposition and parallel solution of blocks taking as a departure point the Bordered-Block Diagonal (BBD) matrix structure. This BBD-parallel approach may give a considerable profit though it is strongly dependent on the system topology. This paper presents a theoretical foundation of the algorithm, its implementation, and numerical complexity analysis in virtue of practical measurements of matrix operations.

Fast Analysis of a Large-Scale Inductive Interconnect by Block-Structure-Preserved Macromodeling

To efficiently analyze the large-scale interconnect dominant circuits with inductive couplings (mutual inductances), this paper introduces a new state matrix, called VNA, to stamp inverse-inductance elements by replacing inductive-branch current with flux. The state matrix under VNA is diagonal-dominant, sparse, and passive. To further explore the sparsity and hierarchy at the block level, a new matrix-stretching method is introduced to reorder coupled fluxes into a decoupled state matrix with a bordered block diagonal (BBD) structure. A corresponding block-structure-preserved model-order reduction, called BVOR, is developed to preserve the sparsity and hierarchy of the BBD matrix at the block level. This enables us to efficiently build and simulate the macromodel within a SPICE-like circuit simulator. Experiments show that our method achieves up to 7× faster modeling building time, up to 33× faster simulation time, and as much as 67× smaller waveform error compared to SAPOR [a second-order reduction based on nodal analysis (NA)] and PACT (a first-order 2×2 structured reduction based on modified NA).

A multilevel unsymmetric matrix ordering algorithm for parallel process simulation

Computer simulation of complex chemical processes is increasingly being used in the design optimization and control of chemical facilities. Industrial-scale modeling involves the solution of large systems of algebraic differential equations. This is very computationally intensive with a large part of the computing time attributed to the repeated solution of large, sparse. unsymmetric systems of linear equations. One way of speeding up the simulation is to solve the linear systems efficiently in parallel by reordering the unsymmetric matrices into a bordered block-diagonal (BBD) form. In this paper a multilevel ordering algorithm is presented. A multilevel technique, which provides a global view, is combined with a Kernighan–Lin algorithm to form an effective unsymmetric matrix ordering algorithm MONET (Matrix Ordering for minimal NET-cut). Numerical results confirm that this algorithm gives ordering of better quality than existing algorithms.

LU decomposition and forward-backward substitution of recursive bordered block diagonal matrices

Tearing methods for large systems have been widely studied and applied over the last decade. Most of the applications used single-level partitioning of a system into subsystems. In the paper, tearing is applied to hierarchically described systems, where each subsystem is itself composed of subsystems, and so on to arbitrary depth. This structure gives rise naturally to ‘recursive’ bordered block diagonal (BBD) matrices, where each diagonal block is itself in the BBD form. Algorithms for LU decomposition and forward and back substitution of such matrices are described.

A survey of third-generation simulation techniques

We present a review of recent work on circuit simulation techniques which are in that they go beyond the Sparse Gauss Elimination, Newton Iteration, Stiff Implicit time integration approach which mark second-generation circuit simulators such as SPICE-II and ASTAP-II. Third generation simulators such as MOTIS, DIANA, and SPLICE have rejected one or more of these principal features in their quest for size and speed capabilities commensurate with the requirements of the VLSI era. We attempt to present a unified treatment of the various and disparate types of third generation simulators based on the concepts of large-scale decomposition theory. In particular we shall describe and classify simulators in terms of the role played by certain matrix forms in their formulation, namely Bordered Block Diagonal (BBD), Bordered Block Triangular (BBT), and Bordered Lower Triangular (BLT).