Boolean Circuit Model Research Articles

Superpolynomial Lower Bounds Against Low-Depth Algebraic Circuits

An Algebraic Circuit for a multivariate polynomial P is a computational model for constructing the polynomial P using only additions and multiplications. It is a syntactic model of computation, as opposed to the Boolean Circuit model, and hence lower bounds for this model are widely expected to be easier to prove than lower bounds for Boolean circuits. Despite this, we do not have superpolynomial lower bounds against general algebraic circuits of depth 3 (except over constant-sized finite fields) and depth 4 (over any field other than F 2 ), while constant-depth Boolean circuit lower bounds have been known since the early 1980s. In this paper, we prove the first superpolynomial lower bounds against algebraic circuits of all constant depths over all fields of characteristic 0. We also observe that our super-polynomial lower bound for constant-depth circuits implies the first deterministic sub-exponential time algorithm for solving the Polynomial Identity Testing (PIT) problem for all small-depth circuits using the known connection between algebraic hardness and randomness.

Towards targeted combinatorial therapy design for the treatment of castration-resistant prostate cancer

BackgroundProstate cancer is one of the most prevalent cancers in males in the United States and amongst the leading causes of cancer related deaths. A particularly virulent form of this disease is castration-resistant prostate cancer (CRPC), where patients no longer respond to medical or surgical castration. CRPC is a complex, multifaceted and heterogeneous malady with limited standard treatment options.ResultsThe growth and progression of prostate cancer is a complicated process that involves multiple pathways. The signaling network comprising the integral constituents of the signature pathways involved in the development and progression of prostate cancer is modeled as a combinatorial circuit. The failures in the gene regulatory network that lead to cancer are abstracted as faults in the equivalent circuit and the Boolean circuit model is then used to design therapies tailored to counteract the effect of each molecular abnormality and to propose potentially efficacious combinatorial therapy regimens. Furthermore, stochastic computational modeling is utilized to identify potentially vulnerable components in the network that may serve as viable candidates for drug development.ConclusionThe results presented herein can aid in the design of scientifically well-grounded targeted therapies that can be employed for the treatment of prostate cancer patients.

Prediction of Pairwise Gene Interaction Using Threshold Logic

The two important problems of computational biology are the modeling of gene regulatory networks and the study of the network structure of complex biological systems. There is an increased use of mathematical and computational theory techniques to solve both these problems. The Boolean circuit model is one of the most popular modeling paradigms used to model gene regulatory networks. In this paper we try to make use of the properties of threshold logic (an alternative to Boolean logic to design digital circuits) to determine the network structure of gene systems. This approach uses the gene-expression data from microarray experiments as input. The proposed method was first used to build the gene network for a set of genes, proteins, and other molecular components based on in silico data. Then, the method was applied to a biological dataset to build the gene regulatory network for a core set of genes associated with melanoma. Some of the interactions found could be verified by earlier biological experiments reported in published literature. Other interactions that could not be validated by existing biological knowledge can provide insights into the investigation of bio-chemical pathways associated with melanoma development.

Non-cancellative Boolean circuits: A generalization of monotone boolean circuits

Cancellations are known to be helpful in efficient algebraic computation of polynomials over fields. We define a notion of cancellation in Boolean circuits and define Boolean circuits that do not use cancellation to be non-cancellative. Non-cancellative Boolean circuits are a natural generalization of monotone Boolean circuits. We show that in the absence of cancellation, Boolean circuits require super-polynomial size to compute the determinant interpreted over GF(2). This non-monotone Boolean function is known to be in P . In the spirit of monotone complexity classes, we define complexity classes based on non-cancellative Boolean circuits. We show that when the Boolean circuit model is restricted by withholding cancellation, P and popular classes within P are restricted as well, but NP and circuit definable classes above it remain unchanged.

Verifying the determinant in parallel

In this paper, we investigate the complexity of verifying problems whose computation is equivalent to the determinant, both in the Boolean arithmetic circuit and in the Boolean circuit model. We observe that for a few problems, there exists an easy (NC 1) verification algorithm. To characterize the harder ones, we define the class of problems that are reducible to the verification of the determinant, under two different reductions, and establish a list of complete problems in these classes. In particular, we prove that computing the rank is equivalent under AC 0 reductions to verifying the determinant. We show in the Boolean case that none of the complete problems can be recognized in NC 1 unless L = NL. On the other hand, we show that for functions, there exists an NC 1 checker even if they are hard to verify, and that they can be extended into functions whose verification is easy.

Comparison of two's complement numbers

The problem of comparing n-bit two's complement numbers is closely related to the problem of detecting whether a carry is generated from the sum of two numbers. A faster solution to the carry generation problem immediately yields a faster solution to the comparison problem. We use a variation of the boolean circuit model to present a new upper bound to the solution of both problems. The new solution uses half-adders and a parallel prefix-and circuit to find the unique significant carry bit, and tristate buffers to pass the value of the significant bit to the output. Two implementations are presented: the bit prefix-and method, which is suitable for small n, and the group prefix-and method, which is just as fast but uses less hardware for moderate to large n. Both methods have simple and regular layouts, and are faster and require less area than existing methods.

Extended Smolensky's method

We give a simple extension of Smolensky's method by replacing Smolensky's concept of U^n_F-completeness by a new definition: F-hardness. An easy consequence of this definition is that F-hard functions do not have constant depth, polynomial size Boolean circuit with Mod_p, where p is the characteristic of F. By this extension, we can explicitly show many functions are hard, we establish a {\em Hardness Lemma} for a class of functions, and characterize when a function over a finite field is hard to compute by a small depth with Mod_p gates. Furthermore, we discuss the difficulties in extending Smolensky's theory over a general ring. While in general the nice relationship between the Boolean circuit model and the algebra of functions representing Boolean functions over a ring collapses, we can still extend the complexity theoretic notions introduced by this extended Smolensky's theory to a ring in order to classify functions over such a ring by their relative complexity. A result states that any representation of <em>Majority</em> over any ring R=Z/(r) for any fixed r in N is hard. This provides a kind of evidence that <em>Majority</em> is not AC^0 reducible to Mod_r.

Four results on the complexity of VLSI computations

We present four results on the complexity of VLSI computations: a) We further justify the Boolean circuit model [Vu, Sa, LS] by showing that it is able to model multi-directional VLSI devices (e.g. pass transistors, pre-charged bus drivers). b) We prove a general cutting theorem for compact regions in R^{d} (d\geq2) that allows us to drop the convexity assumption in lower bound proofs based on the crossing sequence argument. c) We exhibit an \Omega(n^{1/3}) asymptotically tight lower bound on the area of strongly where-oblivious chips for transitive functions. d) We prove a lower bound on the switching energy needed for computing transitive functions.