Body Bias Voltage Research Articles

A 52-to-57 GHz CMOS Phase-Tunable Quadrature VCO Based on a Body Bias Control Technique

This paper presents a 52-to-57 GHz CMOS quadrature voltage-controlled oscillator (QVCO) with a novel I/Q phase tuning technique based on a body bias control method. The QVCO employs an in-phase injection-coupling (IPIC) network comprising four diode-connected FETs for the quadrature phase generation. The I/Q phase error is calibrated by controlling the body bias voltage offset of the QVCO’s four core FETs. This technique effectively covers a wide range of I/Q phase error between −13.4° and +10.7°. It also minimally induces the unwanted variations in the phase noise, current dissipation, and oscillation frequency, which were found to be only 0.4 dB, 0.07%, and 36 MHz, respectively. After the IPIC-QVCO, a phase-tunable two-stage LO buffer employing a 3-bit switched-capacitor bank was added for additional phase tuning, leading to the extension of the phase tuning range up to −22.7–+20.0°. The proposed QVCO is implemented in a 40 nm RF CMOS process. The measured results show that the QVCO covers a frequency band from 52.4 to 57.6 GHz while consuming 26.2 mW. The phase noise and the figure-of-merit of the QVCO are −91.8 dBc/Hz at 1 MHz offset and −172.4 dBc/Hz, respectively. We also realized a fully integrated 55 GHz quadrature RF transmitter employing the phase-tunable QVCO and LO generator. The effectiveness of the proposed phase-tunable LO generator was confirmed by verifying the image rejection ratio (IRR) calibration at the RF output.

A Scalable Body Bias Optimization Method Toward Low-Power CGRAs

Body biasing is one of the critical techniques to realize more energy-efficient computing with reconfigurable devices, such as coarse-grained reconfigurable architectures. Its benefit depends on the control granularity, whereas fine-grained control makes it challenging to find the best body bias voltage for each domain due to the complexity of the optimization problem. This work reformulates the optimization problem and introduces continuous relaxation to solve it faster than previous work based on an integer linear program. Experimental result shows the proposed method can solve the problem within 0.5 s for all benchmarks in any conditions. For a middle-class problem, up to 5.65× speedup and a geometric mean of 2.06× speedup are demonstrated compared to the previous method with negligible loss of accuracy. Besides, we explore finer body bias control considering the power- and area-overhead of an on-chip body bias generator and suggest the most reasonable design saves 66% of energy consumption.

Broadband High-Efficiency Millimeter-Wave Power Amplifiers in 22-nm CMOS FD-SOI with Fixed and Adaptive Biasing

The design of broadband highly-efficient millimeter-wave (mm-Wave) Power Amplifiers (PA) in 22-nm CMOS FD-SOI (fully depleted silicon-on-insulator) is discussed. One design uses fixed biasing while the other utilizes an adaptive biasing network to improve its Power-Added-Efficiency (PAE) in power backoff. These designs aim to cover the key Fifth-Generation (5G) FR2 (Frequency Range 2) band (e.g., from 24.25 GHz to 43.5 GHz). In measurement, the PAs obtain very broadband 3-dB BW, ranging from 19.1 GHz to 46.5 GHz for the fixed-bias design and 18.8 GHz to 41.9 GHz for the adaptively biased design. The adaptively biased design is able to achieve enhanced output 1-dB compression point (OP1dB) and PAE@P1dB because of its adaptive biasing network. Measurements on the fixed-biased PA at 24/28/37/39 GHz yield max. PAE of 22.2/22.4/19.7/19.8%, and POUT,SAT of 14.9/15.3/14.7/14.7 dBm, with OP1dB of 11.8/11.6/12/11.6 dBm, and PAE@P1dB of 14.1/13.4/14.5/13.5%. Measurements on the adaptively biased PA at 24/28/37/39 GHz yield max. PAE of 20.1/15.2/10.3/7.9%, and POUT,SAT of 14.6/14.2/12.5/11.2 dBm, with improved OP1dB of 13.1/12.3/12.1/11.2 dBm, and PAE@P1dB of 19.1/14.4/10.3/7.9%. Data from body bias voltage VB on the PA performance is also presented. These measurement results are compared with post-layout parasitic-extraction (PEX) simulations, and also against other novel silicon broadband mm-Wave PAs in literature.

A High Efficiency Low Noise RF-to-DC Converter Employing Gm-Boosting Envelope Detector and Offset Canceled Latch Comparator

This work presents a high efficiency RF-to-DC conversion circuit composed of an LC-CL balun-based Gm-boosting envelope detector, a low noise baseband amplifier, and an offset canceled latch comparator. It was designed to have high sensitivity with low power consumption for wake-up receiver (WuRx) applications. The proposed envelope detector is based on a fully integrated inductively degenerated common-source amplifier with a series gate inductor. The LC-CL balun circuit is merged with the core of the envelope detector by sharing the on-chip gate and source inductors. The proposed technique doubles the transconductance of the input transistor of the envelope detector without any extra power consumption because the gate and source voltage on the input transistor operates in a differential mode. This results in a higher RF-to-DC conversion gain. In order to improve the sensitivity of the wake-up radio, the DC offset of the latch comparator circuit is canceled by controlling the body bias voltage of a pair of differential input transistors through a binary-weighted current source cell. In addition, the hysteresis characteristic is implemented in order to avoid unstable operation by the large noise at the compared signal. The hysteresis window is programmable by changing the channel width of the latch transistor. The low noise baseband amplifier amplifies the output signal of the envelope detector and transfers it into the comparator circuit with low noise. For the 2.4 GHz WuRx, the proposed envelope detector with no external matching components shows the simulated conversion gain of about 16.79 V/V when the input power is around the sensitivity of −60 dBm, and this is 1.7 times higher than that of the conventional envelope detector with the same current and load. The proposed RF-to-DC conversion circuit (WuRx) achieves a sensitivity of about −65.4 dBm based on 45% to 55% duty, dissipating a power of 22 μW from a 1.2 V supply voltage.

Design of power-efficient CMOS based oscillator circuit with varactor tuning control

This paper presents a low-power, wide tuning range CMOS voltage-controlled oscillator with MCML (MOS current mode logic) differential delay cell. Voltage controlled oscillator (VCO) circuit is designed in TSMC 0.25 μm CMOS process. To achieve the broad frequency range concept of variable capacitance is employed in the proposed VCO circuit. Source/drain tuning voltage (Vtune) and body bias voltage (Vb) of I-MOS varactor are used to achieve variable capacitance at different I-MOS varactor widths (W). The dual control voltage of I-MOS varactor results in a tuning range from 0.528 GHz to 2.014 GHz. VCO's figure of merit (FoM) is 152.13 dBc/Hz with phase noise of −93.77 dBc/Hz at 1 MHz offset from the oscillation frequency. The proposed VCO dissipates maximum power of 3.127 mW.

A self-bias NAND gate and its application to non-overlapping clock generator for extremely low-voltage CMOS LSIs

This paper presents a self-bias NAND (SBNAND) gate and its application to a non-overlapping (NOL) clock generator for extremely low-voltage CMOS LSIs. The SBNAND, consisting of a main NAND gate and feedback inverter, improves the output performance at extremely low supply voltage V DD by controlling the body-bias voltages V BS of the main NAND gate. Measurements of a proof-of-concept chip demonstrated that our proposed NOL clock generator using SBNANDs can operate at the extremely low V DD of 60 mV.

A 61-GHz Rectifier Using Internal Voltage Cancellation and Body-Biasing Techniques in 22-nm FDSOI

This letter presents a millimeter-wave (mm-wave) two-stage rectifier. It is designed to power a backscattering low voltage RFID tag system providing the maximum power conversion efficiency (PCE) at low output voltages. It utilizes the internal voltage cancellation (IVC) scheme as well as forward body-biasing (BB) for internal MOS transistors' threshold compensation. A low voltage charge pump is used to generate the differential body bias voltages. An oscillator with regulated power supply is designed to provide a clock signal to the charge pump at very low voltages. It provides 9% PCE at -13-dBm input power and 33- kΩ equivalent loading. It has also -13-dBm sensitivity for 1-V output voltage for the open load condition.

Body-Biased Multiple-Gate Micro-Electro-Mechanical Relays

Micro-electro-mechanical relays with multiple gate electrodes ( i.e ., multiple input voltage signals), operated with a tunable body bias voltage, are investigated for more compact and energy-efficient implementation of digital logic circuits. Specifically, a relay design with three gate electrodes of equal area is demonstrated to be capable of performing different digital logic functions for the same input operating voltage ( ${V} _{\textbf {DD}}$ ), by adjusting the body bias voltage. Since the lower limit for ${V} _{\textbf {DD}}$ is equal to the switching hysteresis voltage ( ${V} _{\textbf {H}}$ ), the magnitude of ${V} _{\textbf {H}}$ is investigated for different combinations of transitioning input voltage signals. It is found that ${V} _{\textbf {H}}$ is larger for fewer transitioning input voltage signals, i.e. , reduced effective actuation area of the switching input voltage signal. This can set a practical upper limit for the number of independent gates in a single relay.

Analysis of Random Body Bias Application in FDSOI Cryptosystems as a Countermeasure to Leakage-Based Power Analysis Attacks

This paper analyses a novel countermeasure to Leakage Power Analysis Attacks based on the application of a random Body Bias voltage level at the beginning of the encryption process. The countermeasure effectiveness is established through the development of a theoretical model of the Pearson correlation coefficient in the presence of a varying body bias under both noiseless assumptions and in the presence of algorithmic noise, and through simulations on a partial cryptosystem implemented in 28 nm FDSOI technology. A study of the effect of averaging power measurements is also developed and contrasted against Monte Carlo simulations of the countermeasure scheme, effectively providing a floor for the increase in required measurements to identify the secret key.

Decentralized Real-Time Optimization of Voltage Reconfigurable Cloud Computing Data Center

Dynamic Voltage and Frequency Scaling, and Adaptive Body Biasing are increasingly adopted hardware techniques to improve energy efficiency of multi-core servers by adjusting reconfigurable supply and body bias voltages. Existing algorithms cannot fulfill the potential of the techniques because random variations of workload and background traffic can lead to coupling of voltage configurations over time and hinder effective real-time reconfigurations. This paper proposes a new approach which enables multi-core servers to optimize in real-time their configurations under random traffic variations. The approach asymptotically minimizes the time-averaged energy consumption of cloud computing while maintaining platform stability in a fully decentralized fashion. Lyapunov optimization is employed to decouple and separately optimize the voltage configuration, inter- and intra-server offloading schedules among servers and over time. The voltage configuration which is non-convex is proved to increasingly exhibit convexity with growing workloads. The optimality loss from the non-convexity asymptotically diminishes. Simulations show our approach dramatically reduces the power if the cloud is lightly loaded, or converts the power to processing capacity otherwise. Embraced by theoretical breakthroughs, the approach can potentially revolutionize cloud computing.

Design of high efficiency active class E rectifier using PMOS switch for hybrid wireless power transfer

The wireless power transfer (WPT) circuits are very promising to conduct therapy in several conditions especially in neurological stimulation. In the WPT designs, a high efficiency rectification and a DC output regulation are performed simultaneously using active rectifier without the need of an additional regulating circuits. However, the significant ripple appeared at the DC output voltage waveform so that reducing the efficiency of the rectifier. This is due to the application of NMOS as a switching device, where the threshold voltage of NMOS is strongly influenced by the body bias voltage. In this paper, the design of the active class E rectifiers using PMOS switch produces the DC output voltage waveform with an average ripple over 0-100% duty cycle is 16.7%. With simple structure and compact size, this proposed active class E rectifier can be applied for the future Hybrid WPT applications especially in low power operations.

A 42 mV startup ring oscillator using gain-enhanced self-bias inverters for extremely low voltage energy harvesting

This paper presents a ring oscillator (ROSC) capable of operating at an extremely low supply voltage. The proposed ROSC consists of gain-enhanced self-bias inverters. The voltage gain of the proposed inverter is improved by controlling the body bias voltages. Measurements of a prototype chip demonstrated that our proposed ROSC can operate at an extremely low supply voltage of 42 mV.

Body Bias Optimization for Real-Time Systems

The energy of real-time systems for embedded usage needs to be efficient without affecting the system’s ability to meet task deadlines. Dynamic body bias (BB) scaling is a promising approach to managing leakage energy and operational speed, especially for system-on-insulator devices. However, traditional energy models cannot deal with the overhead of adjusting the BB voltage; thus, the models are not accurate. This paper presents a more accurate model for calculating energy overhead using an analytical double exponential expression for dynamic BB scaling and an optimization method based on nonlinear programming with consideration of the real-chip parameter constraints. The use of the proposed model resulted in an energy reduction of about 32% at lower frequencies in comparison with the conventional model. Moreover, the energy overhead was reduced to approximately 14% of the total energy consumption. This methodology provides a framework and design guidelines for real-time systems and computer-aided design.

Performance-aware predictive-model-based on-chip body-bias regulation strategy for an ULP multi-core cluster in 28 nm UTBB FD-SOI

The performance and reliability of Ultra-Low-Power (ULP) computing platforms are adversely affected by environmental temperature and process variations. Mitigating the effect of these phenomena becomes crucial when these devices operate near-threshold, due to the magnification of process variations and to the strong temperature inversion effect that affects advanced technology nodes in low-voltage corners, which causes huge overhead due to margining for timing closure. Supporting an extended range of reverse and forward body-bias, UTBB FD-SOI technology provides a powerful knob to compensate for such variations. In this work we propose a methodology to maximize energy efficiency at run-time exploiting body biasing on a ULP platform operating near-threshold. The proposed method relies on on-line performance measurements by means of Process Monitoring Blocks (PMBs) coupled with an on-chip low-power body bias generator. We correlate the measurement performed by the PMBs to the maximum achievable frequency of the system, deriving a predictive model able to estimate it with an error of 9.7% at 0.7 V. To minimize the effect of process variations we propose a calibration procedure that allows to use a PMB model affected by only the temperature-induced error, which reduces the frequency estimation error by 2.4x (from 9.7% to 4%). We finally propose a controller architecture relying on the derived models to automatically regulate at run-time the body bias voltage. We demonstrate that adjusting the body bias voltage against environmental temperature variations leads up to 2X reduction in the leakage power and a 15% improvement on the global energy consumption when the system operates at 0.7 V and 170 MHz.

The Complete Switching Circuit Design for CPU Joint Body Biasing and Supply Voltage Scaling

The modern CPU technology scaling with increasing transistor density causes an exponential growth of both dynamic and static power dissipations that affecting the microprocessor’s performance. The body bias voltage (VBB) and supply voltage (VDD) extent to decrease to maintain the low power requirements. Joint body biasing and voltage scaling is an efficient technique that reduces the power dissipation of CPUs and high performance digital devices when peak performance is unneeded. Switching networks have become an essential component in the design of digital ICs that require the ability to control and select a specified threshold voltage/body-bias and supply voltages (VTH/VBB-VDD) for the microprocessor chip. This paper presents a complete design of a switching network for joint body biasing and supply voltage scaling (VBB-VDD), which is consistent in allowing compact low power consumption and low temperatures in the core of high-performance processors. The results show the roles and effectiveness of the switching network that adaptively selects the VTH/VBB-VDD sets for different workloads and simulation environments and all temperature ranges.

Voltage-Controlled Oscillator Design Using MOS Varactor

In this work, voltage-controlled ring oscillator (VCO) by employing the three transistors (3T) XOR gates and NMOS varactor load has been reported. Output load has been varied with the application of reverse body bias voltage of NMOS transistor. VCO circuits with 3 and 5 delay stages have been designed. The output frequency is controlled by coarse and fine tuning techniques. The coarse tuning is provided with the variation in supply voltage (VCT) in the range of 1.8 V to 3.3 V. Further, fine tuning has been obtained with variation in reverse substrate bias voltage of NMOS varactor load from 0 to − 1 V. A three-stage VCO design shows output frequency deviation from 340.136 to 628.930 MHz and power consumption ranges from 0.1658 to 1.1285 mW with coarse tuning technique. Frequency deviation from 340.136 to 333.344 MHz and power consumption deviation from 0.1658 to 0.1648 mW have been obtained with fine tuning in three-stage VCO with fixed VCT of 1.8 V. A five-stage VCO design provides the output frequency from 189.035 to 328.947 MHz with power consumption range varying from 0.1698 mW to 1.1364 mW in coarse tuning mode. Moreover, five-stage VCO with fine tuning shows frequency variations from 328.947 to 326.797 MHz with varied power from 1.1364 to 1.1350 mW having the fixed VCT of 3.3 V. Results have been achieved with SPICE in 0.35-µm CMOS technology. An assessment of proposed VCO with previously reported circuits shows improvements in terms of output frequency range and power consumption.

Body Bias Control for Renewable Energy Source with a High Inner Resistance

Sensor nodes used in Internet of Things (IoT) are required to work an extremely long time without replacing the battery. Natural renewable energy such as a solar battery is a hopeful candidate for such nodes. Here, a power model for operating an Silicon on Insulator (SOI) device with a solar battery including a large inner resistance is proposed, and applied to a micro-controller V850E-star and an accelerator CMA-SOTB2. Unlike the ideal case, the maximum operational frequency was achieved with reverse biasing by suppressing the leakage current which decreases the supply voltage. Under the room light with a large inner resistance, the strong reverse bias is effective, while a relatively weak reverse bias is advantageous under the bright light. The proposed model is appeared to be useful to estimate the appropriate body bias voltage both for V850E-star and CMA-SOTB2. In the V850E-star, the estimated operational frequencies were different from the real chip, while they were relatively matched when CMA-SOTB2 was used under the low illuminance.

Digitally Assisted On-Chip Body Bias Tuning Scheme for Ultra Low-Power VLSI Systems

Body bias control is one of the most efficient means to reduce leakage power, adjust process variation, and apply performance boost. However, such control incurs a certain power overhead that has to be reduced, especially in ultra low-power systems. In order to exploit the advantages of body bias control while guaranteeing power efficiency, an on-chip control scheme is required. Conventionally, on-chip body bias control relies on the use of digital–analog converters. However, such analog circuits require a high power supply voltage and an additional power source, resulting in a considerable power overhead and an increased system cost. In this paper, an on-chip “Digitally assisted Automatic Body-bias Tuning” (DABT) scheme for ultra low-power systems is proposed and evaluated. The proposed scheme controls the body bias voltage so as to meet the timing constraints of a given target system. Since DABT is based on “Digitally assisted” circuitries, it can decrease the power supply voltage to near-threshold region and, therefore, a significant amount of power overhead can be reduced. The proposed system is fabricated with the 65-nm silicon on thin box (SOTB) process, a fully depleted silicon on insulator technology. We demonstrate that the chip can achieve the expected functionality, even with 0.35 V of power supply voltage, and with only a few micro watts of power overhead. Moreover, the efficiency of the proposed system is evaluated with a MIPS processor, adopted as a case study. According to the obtained evaluation results, the proposed system can enable 80% of leakage reduction while maintaining the frequency required to meet the timing constraints of the adopted target MIPS processor.

Cryogenic Characterization of 28-nm FD-SOI Ring Oscillators With Energy Efficiency Optimization

Extensive electrical characterization of ring oscillators (ROs) made in high-$\kappa$ metal gate 28nm Fully-Depleted Silicon-on- Insulator (FD-SOI) technology is presented for a set of temperatures between 296 and 4.3K. First, delay per stage ($\tau_P$), static current ($I_{STAT}$), and dynamic current ($I_{DYN}$) are analyzed for the case of the increase of threshold voltage ($V_{TH}$) observed at low temperature. Then, the same analysis is performed by compensating $V_{TH}$ to a constant, temperature independent value through forward body-biasing (FBB). Energy efficiency optimization is proposed for different supply voltages ($V_{DD}$) in order to find an optimal operating point combining both high RO frequencies and low power dissipation. We show that the Energy-Delay product ($EDP$) can be significantly reduced at low temperature by applying a forward body bias voltage ($V_{FBB}$). We demonstrate that outstanding performance of RO in terms of speed ($\tau_P$=37ps) and static power (7nA/stage) can be achieved at 4.3K with $V_{DD}$ reduced down to 0.325V.

Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization

Body bias control is a fundamental technique widely used to provide an efficient tradeoff between leakage power and performance in ultralow-power systems. Therefore, a lot of research about power optimization which provides optimal power supply and body bias voltages has been carried out. However, considering the actual voltage sources, the conventional approaches suffer from limited performance/power control granularity and may lead to degradation in terms of the energy efficiency. Therefore, in this paper, a power optimization method that improves the performance/power control granularity is proposed and evaluated with real processor chips. In the proposed optimization, the body biases for nMOSFET and pMOSFET are controlled independently, while the conventional methods control them uniformly. This increases the number of possible voltage combinations and allows finer target frequency selection leading to lower power consumption than the conventional methods at the cost of the optimization complexity. In order to ease this complexity, the proposed optimization is based on simple power and delay models. The model-based optimization does not require brute force search in the phase of real chip testing; thus, the testing time and cost can be significantly reduced. Since the coefficients of the models are extracted with real chip measurements, the error of the model can be suppressed to a few percent in average. The proposed approach is validated by real chips implemented with a 65-nm fully depleted silicon on insulator technology. The evaluation results show that the proposed optimization is an efficient mean of power reduction for a leakage current dominant chip. In fact, when compared with the conventional method, the proposed approach achieves 9.617% of average power reduction reaching up to 22.77% in the case of the V850 microcontroller.