Board Level Temperature Cycling Research Articles

Development of Wafer Level Package Platform for High Reliability Crossover MCUs

Fan in and fan out wafer level packages are primarily used in the industry for applications in handheld consumer electronic products. The key benefits of wafer level package (WLP) are small form factor, reduced cost, improved electrical and thermal performance. WLP investigated in this study are directly surface mounted on PCB and have no intermediate substrate. Direct mount of package on PCB, leads to significant CTE mismatch between the package and board which stresses the package solder joint, leading to cyclic fatigue induced solder joint cracking. To overcome the solder joint cracking, stiffer solder alloys have been evaluated. However, higher stiffness of the solder alloy shifts the cyclic stress induced failure, from the solder joint to the package metal interconnect layers. Moreover, WLP on advanced silicon node have fragile low-k and extremely low-k back end of line dielectric layers that also crack or delaminate in cyclic fatigue. In this work extensive WLP platform development has been done with following DOE variables; multi-layer package routing, dielectric materials, solder alloys, solder ball pitch and diameter. Developed packages passed and outperformed the following product reliability qualification conditions: high temperature storage life (150°C, 2000 hours), highly accelerated stress test (110°C / 85%RH / Bias, 528 hours), application level temperature cycling ((-40 °C to 125 °C, 600 cycles), board level temperature cycling (-40 °C to 125 °C, 500 cycles) and board level drop test (1500g/0.5ms, 30 drops). Excellent reliability, functional performance, and successful chip package integration was achieved for WLP for crossover MCU products.

CU Wirebond Technology in 16FFC High Performance Automotive Radar Processor with IR Drop Reduction Methodology

High performance automotive radar front-end processors normally use advanced semiconductor packaging such as Flip Chip, fan-in and fan-out wafer level Ball Grid Array (BGA) packages in order to provide superior performance in their applications. However, for a cost effective package in the competitive business market, wirebonded package can also provide similar uncompromised performance. Advanced Cu wirebond technology was evaluated on the 16FFc radar processor. However, the challenge of high voltage drop, also known as IR drop, in 16FFc technology has to be overcome. As wafer technology moves to smaller advanced nodes, the back-end-of-line (BEOL) metal thickness gets thinner, thus increasing the resistance per unit length. Another trend in semiconductor design has been a reduction in operating voltage, meaning that small changes in supply voltage may represent an increasing percentage of the digital swing and potentially lead to incorrect logic values. As current flows through a resistor, the high voltage drop could slow down the circuitry, impact the circuit timing and lead to functional failure. In order to reduce the IR drop in the radar processor when using Cu wirebond, a large quantity of intra-die wires was applied on the 16FFc silicon. IR drop simulation was performed on 3 layout conditions, 0%, 50% and 100% of the intra-die wires. Empirical data was also collected with actual Cu wirebonded samples. The fully populated intra-die wires reduced IR drop by 30%. To enable the reliable performance of the intra-die wires, Stand-off Stitch Bond (SSB) wirebond technology was introduced within the package. The development and reliability evaluation was conducted for Cu wirebonding on 16FFc automotive radar processor of 30mm2 die size in a 14mm x14mm 2-layer substrate BGA package. Wirebond recipe was developed based on detailed Design of Experiment to establish bonding parameters for both standard wires and the intra-die wires. Packages were tested per AEC Grade 1 and AEC Q006 qualifications requirements. All results from package reliability assessments passed with no abnormality. Board level temperature cycling reliability for the BGA package with the four depopulated corner solder balls was evaluated with results surpassing NXP requirement for AEC Grade 1. This paper will present the results and analysis from (1) IR drop simulation and empirical data collection, (2) wirebond development and reliability of standard and intra-die wires on 16FFc Silicon, and (3) board level reliability of a BGA package with four depopulated corner solder balls.

Development of high performance flip chip ball grid array (FCBGA) packages for automotive application processors

Automobiles have witnessed rapid proliferation of infotainment, driver assistance and autonomous driving features which have led to significant increase in semiconductor content per car. However, this has also required increased integration of device functionality to meet the new automotive requirements for in-vehicle networking, autonomous driving, infotainment, and sensor integration. Advance technology/packages are needed to provide ideal solutions for automotive grade reliability, high electrical performance, and multi-function integration for automotive application processors. To address these requirements, innovative packages including Flip Chip Ball Grid Array (FCBGA) are the potential solutions. In this study FCBGA packages are developed for automotive processor application and qualified for AEC2 qualification tier. To achieve higher performance and reliability, different package substrate materials such as core dielectric and build-up dielectric were evaluated. Mechanical modelling and simulation of package reliability and influence of key material properties such as coefficient of thermal expansion (CTE), modulus of elasticity (E) and glass transition temperature (Tg) was used to provide guidance for the selection of substrate and assembly materials. Developed packages met all the product performance requirements and passed package qual conditions of high temperature storage life (150°C, 500 hours), temperature cycling (-55 °C to 125 °C, 1000 cycles), temperature humidity bias (85 °C, 85% RH, 1000 hours) and board level temperature cycling (-40 °C to 125 °C, 1000 cycles).

Board Level Reliability of Flipchip Package

In the world of electronic materials, solder is a critical material that plays an important role in the first level (silicon to package substrate) and second level (package to printed circuit board) interconnection. As a joining material in electronic assemblies, solder provides electrical and mechanical connections. The increasing need for reliable electronic devices for harsh environment triggers the need for reliable solder joints. This study focuses on reliability of second level interconnections between package and printed circuit boards. Board level temperature cycling and mechanical drop performance of a 15 mm x 15 mm FCBGA test vehicle were evaluated with different package construction (lidded vs non-lidded), and BGA solder alloys (SA1, SA2, and SA3). Daisy chain packages were assembled on 1.0 mm thick PCB. Mounted units were thermally cycled between from -40C to 125C. Additional samples were evaluated in mechanical drop test conditions following JEDEC standards. Results showed that packages with SA2, and SA3 BGA had significantly higher board-level thermal cycling life compared to SA1. The best drop performance was achieved with SA1 solder. The performance trend among different solder alloys was found to be similar between lidded vs non lidded package. However, lidded package showed improved board-level reliability performance compared to a non-lidded package.

Numerical Implementation of a Unified Viscoplastic Model for Considering Solder Joint Response under Board-Level Temperature Cycling

An implicit integration scheme was developed for simulating the viscoplastic constitutive behavior of Sn3.0Ag0.5Cu solder and programmed into a user material subroutine of the finite element software ANSYS. The numerical procedure first solves the essential state variables by using a three-level iterative procedure, and updates the remaining stress and state variables accordingly. The numerical implementation was applied to consider the responses of solder joints in an electronic assembly under temperature cycling condition. The viscoplastic strain energy density accumulation over one temperature cycle was identified as a feasible parameter for evaluating the thermomechanical reliability of the solder joints.

Solder-Joint Reliability of BGA Packages in Automotive Applications

The solder-joint interconnect between an IC component and the PCB (printed circuit board) is a critical link in the system overall reliability. Trends in the automotive market are driving increased focus on solder-joint performance: (1) increasing electronics content for new functions, especially for ADAS (advanced driver-assistance systems), (2) use in safety critical systems and sub-systems, (3) decreasing interconnect pitches which reduces the stand-off and available solder, (4) increasing industry reliability expectations, and (5) package variations (ex. multi-die). In particular, BGA (Ball Grid Array) packages are used throughout the vehicle across various systems including engine control, braking, communication, infotainment, and radar to name only a few. Among these, under-the-hood applications often require high sustained operating temperatures and many heating/cooling cycles during the vehicle lifetime. The reliability of these interconnects is routinely assessed by cyclical thermal stress (temperate cycling) of components mounted to boards. While AEC (Automotive Electronics Council) offers no standards for solder-joint testing (for example, board level reliability criteria is not included in the AEC Q100 “Failure Mechanism Based Stress Test Qualification for Integrated Circuits”), IPC 9701A “Performance Test Methods and Qualification Requirements for Surface Mount Solder Attachments” can be followed. For automotive under-the-hood the specified cycle range is 40°C to 125°C (TC3). This paper summarizes the BL-TC (board level temperature cycle) performance of various BGA packages used in automotive applications. In all cases the test vehicle packages were daisy-chain versions of production devices, while maintaining critical features such as BGA footprint, physical dimensions, BOM (bill of materials), die size and thickness and substrate layer metal densities. All used Pb-free solders for both the BGA solder ball and the paste printed onto the PCB. The PCB designs were complementary to the packages establishing daisy-chain connections winding through the PCB, the solder-joint and package substrate. Each chain (net) was continuously monitored in situ during cycling. An event detector logged a failure when a net resistance exceeded 300 ohms. Wirebonded and flip chip packages were studied, ranging in size from 10mm to 29mm with BGA pitches including 0.65mm, 0.80mm and 1.00mm. In addition to these primary attributes, various other factors were found to alter the solder-joint lifetimes. For example, increasing BGA pad and solder sphere diameters improved solder-joint lifetime, but increasing the PCB pad diameter often did not. Among solder materials, eutectic SnAg typically showed longer lifetimes than other high Ag SAC alloys such as SAC305 and SAC405. The addition of Bi to the SAC alloy showed promise for further improvements. Other factors that were studied include die thickness, die size, and BGA pad finish. Both mechanical cross-section and dye penetrant analysis (dye-and-pry) were employed for failure analysis, enabling study of crack propagation and crack location within the solder-joint. Additionally, failure location (failing solder-joint) was identified for each as package corner, under the die edge, or package center in a predictable pattern depending on the package type. Examined in total, two opposing trends will force future innovation. Industry reliability requirements continue to drive expectations (i.e. cycles to failure) higher, while increasing package size and decreasing pitch will naturally reduce the solder-joint lifetimes. Solutions will be found in package design, package material and solder selections.

Design of Experiments for Board-Level Solder Joint Reliability of PBGA Package Under Various Manufacturing and Multiple Environmental Loading Conditions

A design of experiments was conducted to determine the reliability of plastic ball grid array packages under various manufacturing and multiple environmental loading conditions. Parameters included conformal coating methods, underfill, solder mask defined, and non-solder mask defined pads. Board-level temperature cycling, vibration, and combined temperature cycling and vibration testing were performed to quantify the reliability and identify preferred design parameters. Through the main effects and interaction analysis, test results show underfill is the key parameter related to the solder joint reliability improvement. Conformal coat method and printed circuit board pad design are not main effects on solder joint reliability. No interactive relationship exists among these three factors under temperature cycling loading, but some interactive relationship between printed circuit board pad type and the conformal coating method exists under vibration and combined loading conditions.

Solder joint reliability of TFBGA assemblies with fresh and reworked solder balls

In this article, the solder joint reliability of thin and fine-pitch BGA (TFBGA) with fresh and reworked solder balls is investigated. Both package and board level reliability tests are conducted to compare the solder joint performance of test vehicle with fresh and reworked solder balls. For package level reliability test, ball shear test is performed to evaluate the joint strength of fresh and reworked solder balls. The results show that solder balls with rework process exhibit higher shear strength than the ones without any rework process. The results also exhibit that the different intermetallic compound (IMC) formation at solder joints of fresh and reworked solder balls is the key to degradation of shear strength. For board level reliability tests, temperature cycling and bending cyclic tests are both applied to investigate the fatigue life of solder joint with fresh and reworked solder balls. It is observed that package with reworked solder ball has better fatigue life than the one with fresh solder ball after temperature cyclic test. As for bending cyclic test, in addition to test on as-assembled packages, reworked and fresh samples are subjected to heat treatment at 150 °C for 100 h prior to the bending cyclic test. The purpose is to let Au–Ni–Sn IMC resettle at solder joints of fresh solder ball and examine the influence of Au–Ni–Sn IMC on the fatigue life of solder joints (Au embrittlement effect). The final results confirm that reworked solder balls have better reliability performance than fresh one since Au embrittlement dose exist at fresh solder ball.