Block-based Neural Network Research Articles

Landslide susceptibility mapping using hybridized block modular intelligence model

Landslide susceptibility map (LSM) provide useful tool for decision makers in hazard mitigation concerns. In the present paper, a novel hybrid block-based neural network model (HBNN) for the purpose of producing high-resolution LSM was developed. This hybrid approach was found through the mixture of expert modular structures and divide-and-conquer strategy incorporated with genetic algorithm (GA). The introduced HBNN then was applied on southern part of Guilan province (north of Iran) using 14 causative factors covering topographic and geomorphologic features, and geological and tectonical factors as well as hydrology, land data, and climate conditions. The landslide inventory map was provided using a synergy work from monitored events, interpretation of aerial photographs, and carried out geotechnical investigations in the area as well as field surveys. To insight, the predictability of proposed HBNN was compared with two developed models using multilayer perceptrons (MLPs) and generalized feed forward neural network (GFFN). The generated LSM was validated using receiver operating characteristic (ROC) curves, statistical error indices, and sensitivity and weight analyses as well as monitored landslides. Based on the compared metrics, HBNN with 86.52% and 90.15% in prediction and success rate as well as 89.36% for precision-recall curve demonstrated more consistent tool for future landslide susceptibility zonation. This implies on capability of developed HBNN in producing higher resolution and more reliable LSM for urban and land-use planners.

A Dynamically Reconfigurable BbNN Architecture for Scalable Neuroevolution in Hardware

In this paper, a novel hardware architecture for neuroevolution is presented, aiming to enable the continuous adaptation of systems working in dynamic environments, by including the training stage intrinsically in the computing edge. It is based on the block-based neural network model, integrated with an evolutionary algorithm that optimizes the weights and the topology of the network simultaneously. Differently to the state-of-the-art, the proposed implementation makes use of advanced dynamic and partial reconfiguration features to reconfigure the network during evolution and, if required, to adapt its size dynamically. This way, the number of logic resources occupied by the network can be adapted by the evolutionary algorithm to the complexity of the problem, the expected quality of the results, or other performance indicators. The proposed architecture, implemented in a Xilinx Zynq-7020 System-on-a-Chip (SoC) FPGA device, reduces the usage of DSPs and BRAMS while introducing a novel synchronization scheme that controls the latency of the circuit. The proposed neuroevolvable architecture has been integrated with the OpenAI toolkit to show how it can efficiently be applied to control problems, with a variable complexity and dynamic behavior. The versatility of the solution is assessed by also targeting classification problems.

Block-Based Neural Network Optimization with Manageable Problem Space

Block-Based Neural Network Optimization with Manageable Problem Space

A Study on Block-Based Neural Network Equalization in TDMR System With LDPC Coding

To achieve a high track density, two-dimensional magnetic recording (TDMR) is combined with shingled magnetic recording (SMR). SMR makes it possible to record 1 bit on a few grains. However, the performance will be remarkably deteriorated by the increased media noise, the inter-track and inter-symbol interference (ITI and ISI). Therefore, the application of effective equalization and error control coding are required. In this paper, we investigate a simple block-based neural network equalizer (NNE) that mitigates the influence of ITI and ISI. We compare the equalization effects of the NNE and a conventional 2-D equalizer with low-density parity-check (LDPC) coding based on a random Voronoi grain media model. Simulation results show the proposed block-based NNE achieves better bit error rate performance than the conventional 2-D linear equalizer followed by the a posteriori probability (APP) detector and a sum-product (SP) decoder. In addition, we find the block-based NNE is sensitive to write errors.

High performance Block-Based Neural Network Model by pipelined parallel communication

High performance Block-Based Neural Network Model by pipelined parallel communication

A Learning Method for Block‐Based Neural Networks with Structure Search Based on the Least Number of Routes

SUMMARYIn recent years, a study of evolvable hardware (EHW) which can adapt to new an unknown environment attracts much attention among hardware designers. EHW is reconfigurable hardware and can be implemented combining reconfigurable devices such as FPGA (Field Programmable Gate Array) and evolutionary computation such as Genetic Algorithms (GAs). As such research of EHW, Block‐Based Neural Networks (BBNNs) have been proposed. BBNNs have simplified network structures and their weights and network structure can be optimized at the same time using GAs. The learning of BBNNs without constraint of network structure is, however, not efficient because the degree of difficulty of learning depends on network structures. In this paper, we proposed a new evaluation index of network structures for BBNNs based on the least number of routes which are from inputs to outputs, and apply it to the structure search. The learning of BBNNs is efficiently executed with structure constraint condition based on the proposed index because the network structures which are difficult to learn are excluded. In order to evaluate the proposed method, we apply it to XOR, 3 bit‐parity, square function approximation, contact lenses fitting, Fisher's iris classification, and Wine classification. Results of computational experiments indicate the validity of the proposed method.

ブロック構造パルスニューラルネットワークにおける誤差逆伝播法のハードウェア実装

ブロック構造パルスニューラルネットワークにおける誤差逆伝播法のハードウェア実装

最小経路数に基づく構造探索を導入したブロック構造ニューラルネットワーク学習法

最小経路数に基づく構造探索を導入したブロック構造ニューラルネットワーク学習法

A new personalized ECG signal classification algorithm using Block-based Neural Network and Particle Swarm Optimization

Abstract The purpose of this paper is the classification of ECG heartbeats of a patient in five heartbeat types according to AAMI recommendation, using an artificial neural network. In this paper a Block-based Neural Network (BBNN) has been used as the classifier. The BBNN is created from 2-D array of blocks which are connected to each other. The internal structure of each block depends on the number of incoming and outgoing signals. The overall construction of the network is determined by the moving of signals through the network blocks. The Network structure and the weights are optimized using Particle Swarm Optimization (PSO) algorithm. The input of the BBNN is a vector which its elements are the features extracted from the ECG signals. In this paper Hermit function coefficient and temporal features which have been extracted from ECG signals, create the input vector of the BBNN. The BBNN parameters have been optimized by PSO algorithm which can overcome the possible changes of ECG signals from time-to-time and/or person-to-person variations. Therefore the trained BBNN has an unique structure for each person. The performance evaluation using the MIT-BIH arrhythmia database shows a high classification accuracy of 97%.

Optimization of structure and system latency in evolvable block-based neural networks using genetic algorithm

Abstract This paper proposes a novel optimization method that utilizes a multi-population parallel genetic algorithm (GA) to simultaneously optimize the structure and system latency of evolvable block-based neural networks (BbNNs). In the past, BbNNs have been successfully deployed for various kinds of classification problems with promising results. However, existing BbNN architectures do not explicitly model or optimize the latency of the system. Optimization of system latency is important, because it improves performance, reduces power consumption, and allows a more deterministic behavior that is needed for recurrent modes. The BbNN hardware model proposed in this paper is implemented as a synchronous architecture with registered outputs. This architecture will permit the system latency to be deterministic. To facilitate the automated layout of the neuron block interconnects within the BbNN structure, an array interconnect algorithm is presented. The proposed latency-optimized BbNN is implemented in hardware, and the architecture resembles mobile devices with integrated graphics processing units (GPUs). The hardware implementation is verified and analyzed using various case studies. The power consumption of our prototyping platform was measured, and it is shown that approximately 364 nJ of energy can be saved for every computational cycle (latency) reduced. All presented case studies show that the proposed BbNN model provides an optimal latency value while still matching the high accuracy reported in previous works.

Hardware implementation of evolvable block-based neural networks utilizing a cost efficient sigmoid-like activation function

This paper presents the hardware implementation of an evolvable block-based neural network that utilizes a novel and cost efficient sigmoid-like activation function. Evolvable block-based neural networks (BbNNs) feature simultaneous optimization of structure, and viable implementation in reconfigurable digital hardware such as field programmable gate arrays (FPGAs). Efficient hardware implementation of BbNN structures is the primary goal of this paper. Various aspects of BbNN modeling and design considerations are presented. The neuron blocks are designed with properly described methodology, using only a single multiplier each, and implement a cost efficient sigmoid-like activation function. A novel method of reusing the multiplier to smoothly approximate a hyperbolic tangent (tanh) function to be used as the activation function for the neuron blocks is also presented. This is an important contribution, because a sigmoid-like activation function is provided at almost no additional cost. The neuron blocks are very cost efficient in terms of logic utilization when compared to the previous work. The BbNN is designed as an system-on-chip (SoC), and is functionally verified and tested on several case studies. The system performance allows real-time classification, and executes up to 410×faster than embedded software.

Industrial Application of Evolvable Block-Based Neural Network to Hypoglycemia Monitoring System

Insulin-dependent diabetes mellitus is classified as type 1 diabetes mellitus (T1DM), and it can be further classified as immune-mediated or idiopathic. It is dangerous and can result in unconsciousness, seizures, and even sudden death. The most common physiological parameters to be effected from a hypoglycemic reaction are heart rate and corrected QT interval of the electrocardiogram (ECG) signal. Considering the correlation between physiological parameters of an ECG signal and the status of hypoglycemia, a noninvasive hypoglycemia monitoring system is tested and introduced by proposing a hybrid particle-swarm-optimization-based block-based neural network (BBNN) algorithm. The proposed BBNN model offers advantages over conventional neural networks by performing the simultaneous optimization of both structure and weights. The hybrid particle swarm optimization with wavelet mutation searches for optimized structure and network parameters through particle information over a search space. All the actual data sets of 15 T1DM children were collected at the Department of Health, Government of Western Australia. Several experiments showed that the proposed BBNN performed well in terms of better sensitivity and specificity.

Evolvable Rough-Block-Based Neural Network and its Biomedical Application to Hypoglycemia Detection System

This paper focuses on the hybridization technology using rough sets concepts and neural computing for decision and classification purposes. Based on the rough set properties, the lower region and boundary region are defined to partition the input signal to a consistent (predictable) part and an inconsistent (random) part. In this way, the neural network is designed to deal only with the boundary region, which mainly consists of an inconsistent part of applied input signal causing inaccurate modeling of the data set. Owing to different characteristics of neural network (NN) applications, the same structure of conventional NN might not give the optimal solution. Based on the knowledge of application in this paper, a block-based neural network (BBNN) is selected as a suitable classifier due to its ability to evolve internal structures and adaptability in dynamic environments. This architecture will systematically incorporate the characteristics of application to the structure of hybrid rough-block-based neural network (R-BBNN). A global training algorithm, hybrid particle swarm optimization with wavelet mutation is introduced for parameter optimization of proposed R-BBNN. The performance of the proposed R-BBNN algorithm was evaluated by an application to the field of medical diagnosis using real hypoglycemia episodes in patients with Type 1 diabetes mellitus. The performance of the proposed hybrid system has been compared with some of the existing neural networks. The comparison results indicated that the proposed method has improved classification performance and results in early convergence of the network.

A Structure Learning Method for Block-Based Neural Networks

A Structure Learning Method for Block-Based Neural Networks

A parallel genetic algorithm for adaptive hardware and its application to ECG signal classification

This paper presents a parallel genetic algorithm (GA) called the cellular compact genetic algorithm (c-cGA) and its implementation for adaptive hardware. An adaptive hardware based on the c-cGA is proposed to automate real-time classification of ECG signals. The c-cGA not only provides a strong search capability while maintaining genetic diversity using multiple GAs but also has a cellular-like structure and is a straight-forward algorithm suitable for hardware implementation. The c-cGA hardware and an adaptive digital filter structure also perform an adaptive feature selection in real time. The c-cGA is applied to a block-based neural network (BbNN) for online learning in the hardware. Using an adaptive hardware approach based on the c-cGA, an adaptive hardware system for classifying ECG signals is feasible. The proposed adaptive hardware can be implemented in a field programmable gate array (FPGA) for an adaptive embedded system applied to personalised ECG signal classifications for long-term patient monitoring.

Clasificación de Granos de Café usando FPGA

Este artículo presenta el desarrollo de un sistema para la clasificación de granos de café, según la etapa de maduración, utilizando Redes Neuronales Artificiales (RNAs). Como herramienta de clasificación se utilizaron dos estructuras de RNAs, Perceptrón Multi-Capa (MLP) y el modelo de red neuronal basado en bloques (BBNN). La estructura MLP fue diseñada e implementada sobre C++ usando el algoritmo de aprendizaje con retro-propagación del error. Para aumentar la velocidad de ejecución de la RNA se implementó bajo dispositivos electrónicos utilizando su paralelismo natural. El modelo BBNN consiste en un arreglo bidimensional de bloques fundamentales y pesos enteros, dirigidos a la fácil implementación sobre dispositivos electrónicos configurables como los arreglos de compuerta programable por campo (FPGAs). La optimización de la estructura usa un algoritmo genético. Esta estructura ha sido implementada y sintetizada sobre la tarjeta Altera Flex 10K FPGAs. El porcentaje de efectividad para la estructura MLP fue 91.7% y para el modelo BBNN fue 89.5%.

Evolvable Block-Based Neural Network Design for Applications in Dynamic Environments

Dedicated hardware implementations of artificial neural networks promise to provide faster, lower-power operation when compared to software implementations executing on microprocessors, but rarely do these implementations have the flexibility to adapt and train online under dynamic conditions. A typical design process for artificial neural networks involves offline training using software simulations and synthesis and hardware implementation of the obtained network offline. This paper presents a design of block-based neural networks (BbNNs) on FPGAs capable of dynamic adaptation and online training. Specifically the network structure and the internal parameters, the two pieces of the multiparametric evolution of the BbNNs, can be adapted intrinsically, in-field under the control of the training algorithm. This ability enables deployment of the platform in dynamic environments, thereby significantly expanding the range of target applications, deployment lifetimes, and system reliability. The potential and functionality of the platform are demonstrated using several case studies.

パルスニューロンモデルを用いたブロック構造ニューラルネットワーク

パルスニューロンモデルを用いたブロック構造ニューラルネットワーク

Block-Based Neural Networks for Personalized ECG Signal Classification

This paper presents evolvable block-based neural networks (BbNNs) for personalized ECG heartbeat pattern classification. A BbNN consists of a 2-D array of modular component NNs with flexible structures and internal configurations that can be implemented using reconfigurable digital hardware such as field-programmable gate arrays (FPGAs). Signal flow between the blocks determines the internal configuration of a block as well as the overall structure of the BbNN. Network structure and the weights are optimized using local gradient-based search and evolutionary operators with the rates changing adaptively according to their effectiveness in the previous evolution period. Such adaptive operator rate update scheme ensures higher fitness on average compared to predetermined fixed operator rates. The Hermite transform coefficients and the time interval between two neighboring R-peaks of ECG signals are used as inputs to the BbNN. A BbNN optimized with the proposed evolutionary algorithm (EA) makes a personalized heartbeat pattern classifier that copes with changing operating environments caused by individual difference and time-varying characteristics of ECG signals. Simulation results using the Massachusetts Institute of Technology/Beth Israel Hospital (MIT-BIH) arrhythmia database demonstrate high average detection accuracies of ventricular ectopic beats (98.1%) and supraventricular ectopic beats (96.6%) patterns for heartbeat monitoring, being a significant improvement over previously reported electrocardiogram (ECG) classification results.

Evolutionary Construction of Block-Based Neural Networks in Consideration of Failure

Evolutionary Construction of Block-Based Neural Networks in Consideration of Failure