Black Phosphorus FETs Research Articles

Effect of the surface oxide layer on the stability of black phosphorus

It has been a long-standing challenge to produce air-stable few-layer black phosphorus (BP) because BP degrade rapidly in ambient atmosphere. Here we demonstrate that the pristine BP with ten layers or more possesses a strong stability and can be stored in air for two weeks. The physical mechanism can be ascribed to the native phosphorus oxide formed on the surface, which act as a stable and protective capping layer and prevent the underlying layer from further oxidation. The pristine 10-layer BP FET device can maintain a high mobility value of around 220 cm2 V-1s−1 in air for 2 weeks. By contrast, the plasma-induced phosphorus oxide is not dense or robust enough to protect the underlying sample from oxidation. These results suggest that the density of the oxide layer on the surface plays a vital role in the stability of BP flakes. This work offers new perspectives for probing the stability of BP based electronic and optoelectronic devices.

A Physics-Based Compact Model for Ultrathin Black Phosphorus FETs—Part II: Model Validation Against Numerical and Experimental Data

In the first part of this article, a physics-based surface-potential compact model to describe current-voltage (I-V) relationship in few-layered ambipolar black phosphorus (BP) transistors is presented. The proposed model captures the essential physics of thin-film BP FETs by accounting for the effects of: 1) in-plane band-structure anisotropy in BP, as well as the asymmetry in electron and hole current conduction characteristics; 2) nonlinear Schottky-type source/drain contact resistances; 3) interface traps; 4) ambipolar current conduction in the device using two separate quasi-Fermi levels for electrons and holes; and 5) the effect of temperature on the model parameters. In this article, the model is validated against measured data of back-gated BP transistors with gate lengths of 1000 and 300 nm with the BP thickness of 7.3 and 8.1 nm and for the temperature range of 200-298 K. We also validate the model against numerical TCAD data of BP transistors with channel lengths of 300 and 600 nm and BP thickness of 6 nm. The model is also applied to unipolar 2-D FETs with channel materials, such as MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and WSe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> . Compared with prior BP FET models that are mainly suited for near-equilibrium transport and room-temperature operation, the model developed here shows excellent agreement with experimental and numerical data over broad bias and temperature range.

A Physics-Based Compact Model for Ultrathin Black Phosphorus FETs—Part I: Effect of Contacts, Temperature, Ambipolarity, and Traps

We report a physics-based surface-potential compact model to describe current–voltage ( $I$ – $V$ ) relationship in a few-layered ambipolar black phosphorus (BP) transistors. To model the device electrostatics, the 2-D density of states of carriers and Fermi–Dirac statistics are used, while carrier transport is described using the drift-diffusion formalism. The model also comprehends the effects of interface traps and voltage-dependent Schottky-type source/drain contact resistances. Compared with prior BP FET models that are mainly suited for near-equilibrium transport and room-temperature operation, the model developed here is applicable over broad bias and temperature range. Validation of the model against measurement data of BP transistors with gate lengths 300–1000 nm and operating temperature from 200–298 K is demonstrated in a companion article.

Negative Capacitance Black Phosphorus Transistors With Low SS

Negative capacitance (NC) shows great potential to enable transistors with the steeper slope, which is very useful for voltage/power applications. Black phosphorus (BP) is theoretically predicted as good channel materials for NC-FETs. However, the experimental demonstration of BP has so far remained elusive. Here, for the first time, NC transistors based on BP have been demonstrated. By connecting to a 20-nm HfZrO ferroelectric capacitor, both two types of BP transistors show lower subthreshold slope (SS). For 5-nm AlOx BP transistor, the SS decreases from 200 to 104 mV/dec. The experimental results are analyzed with the BP-NCFET model, and the calculated transfer curve can fit well with the experimental curve, which proves the validation of the model. Our work sheds light on using NC BP FETs for low-power flexible electronics applications.

Double carrier transport in electron-doped region in black phosphorus FET

Double carrier transport has been observed in thin film black phosphorus (BP) field effect transistor devices in the highly electron-doped region. BP thin films with a typical thickness of 15 nm were encapsulated by hexagonal boron nitride thin films to avoid degradation by air exposure. Their Hall mobility reached 5300 cm2/V s and 5400 cm2/V s at 4.2 K in the hole- and electron-doped regions, respectively. The gate voltage dependence of conductivity exhibits an anomalous shoulder structure in the electron-doped region. In addition, at gate voltages above the shoulder, the magnetoresistance changes to positive, and there appears an additional slow Shubnikov-de Haas oscillation. These results strongly suggest the appearance of second carriers, which originate from the second subband with a localized band edge.

First-Principles-Based Quantum Transport Simulations of Monolayer Indium Selenide FETs in the Ballistic Limit

We investigate the ballistic performance of monolayer indium selenide (InSe) n-type FETs, benchmarking with monolayer WS2, WSe2, and black phosphorus FETs. We utilize first-principles-based quantum transport simulations employing density functional theory and nonequilibrium Green’s function. The transfer characteristics, subthreshold swing, and drain-induced barrier lowering of InSe FETs are assessed and compared with those of the benchmarks. Our comparison of InSe FETs to the benchmark transistors reveals that InSe transistors are competitive in ON-state performance, but the short-channel effects in ultrascaled InSe FETs need to be suppressed. InSe FETs are favorable for high-performance applications rather than low power ones.

Monolayer Transistor SRAMs

Monolayer heterojunction FETs based on vertical heterogeneous transition metal dichalcogenides (TMDCFETs) and planar black phosphorus FETs (BPFETs) have demonstrated excellent subthreshold swing, high I ON I OFF , and high scalability, making them attractive candidates for post-CMOS memory design. This article explores TMDCFET and BPFET SRAM design by combining atomistic self-consistent device modeling with SRAM circuit design and simulation. We perform detailed evaluations of the TMDCFET/BPFET SRAMs at a single bitcell and at SRAM array level. Our simulations show that at low operating voltages, TMDCFET/BPFET SRAMs exhibit significant advantages in static power, dynamic read/write noise margin, and read/write delay over nominal 16nm CMOS SRAMs at both bitcell and array-level implementations. We also analyze the effect of process variations on the performance of TMDCFET/BPFET SRAMs. Our simulations demonstrate that TMDCFET/BPFET SRAMs exhibit high tolerance to process variations, which is desirable for low operating voltages.

The Role of Air Adsorption in Inverted Ultrathin Black Phosphorus Field-Effect Transistors.

Few-layer black phosphorus (BP) attracts much attention owing to its high mobility and thickness-tunable band gap; however, compared with the commonly studied transition metal dichalcogenides (TMDCs), BP has the unfavorable property of degrading in ambient conditions. Here, we propose an inverted dual gates structure of ultrathin BP FET to research the air adsorption on BP. In fabrication process of back-gate BP FET, BP was transferred directly onto a wafer covered with electrodes. Thus, we can exclude the BP degradation during the process of electrodes fabrication, such as electron beam lithography (EBL) and thermal evaporation process. Furthermore, without any electrode covering BP, BP could be in full contact with the air; then the accurate effect of the air adsorption on BP can be researched in detail. The results clearly show that annealing can remove the p-doping resulted from the metastable oxygen adsorbed on the surface of BP, but the adsorption can be restored in a few hours exposure. In addition, both back and top gate inverted BP FETs exhibit a favorable performance. Therefore, this inverted structure is also an optional structure to reduce the influence of the instability of BP devices.

Long-Term Stability and Reliability of Black Phosphorus Field-Effect Transistors

Black phosphorus has been recently suggested as a very promising material for use in 2D field-effect transistors. However, due to its poor stability under ambient conditions, this material has not yet received as much attention as for instance MoS2. We show that the recently demonstrated Al2O3 encapsulation leads to highly stable devices. In particular, we report our long-term study on highly stable black phosphorus field-effect transistors, which show stable device characteristics for at least eight months. This high stability allows us to perform a detailed analysis of their reliability with respect to hysteresis as well as the arguably most important reliability issue in silicon technologies, the bias-temperature instability. We find that the hysteresis in these transistors depends strongly on the sweep rate and temperature. Moreover, the hysteresis dynamics in our devices are reproducible over a long time, which underlines their high reliability. Also, by using detailed physical models for oxide traps developed for Si technologies, we are able to capture the channel electrostatics of the black phosphorus FETs and determine the position of the defect energy band. Finally, we demonstrate that both hysteresis and bias-temperature instabilities are due to thermally activated charge trapping/detrapping by oxide traps and can be reduced if the device is covered by Teflon-AF.

(Invited) Effects of Van Der Waals Interaction in 2D Layered Material FETs and Their Device Performance Benchmark

Most of the current electronic devices compose of millions of transistors that are packed into an area smaller than a fraction of a fingernail and the continuing improvement of consumer devices are driven by the miniaturization of these devices for the past four decades. By shrinking down the sizes of these electronic components, device performances are improved such as reducing power consumption and increasing device speed, as well as other enhancements such as complex functionalities, portability and cost reduction. This leads to the wide-spread usage of electronic devices in every aspect of society, from increasing productivity in automations in manufacturing industries to vital signs monitoring in biomedical sector. As the channel length of silicon transistors, the work horse of modern electronic devices, shrank from few hundred micrometres to tens of nanometres, new challenges had surfaced which necessitated the development of novel device designs and fabrication techniques, such as ultrathin body (UTB) technology, high-k gate dielectrics, strained channel material and tri-gate design in FinFET. While these advances in electronics have been instrumental in sustaining the Moore’s law for the past decade, further improvement in the coming years would require adoption of novel materials and transistor geometries. Since the successful demonstration of thermodynamically stable two dimensional (2D) graphene by Novoselov, et al. and Berger, et al. in 2004, and the subsequent studies on the properties of graphene and other layered 2D materials, the idea of using these atomically thin layers as the channel material in field-effect devices has been investigated extensively. A wide range of 2D materials have been proposed and studied, including graphene, transition metal dichalcogenides (TMDs), hexagonal boron nitride (h-BN) and black phosphorus (BP), as well as 2D version of traditional material such as silicene and germanene. Experimentally, most of these materials applied into FET type devices haven been demonstrated and theoretically, it has also been intensively studied their FET performance down to sub 10nm. However, the devices simulated thus far had been restricted to double gated structures, which have not been demonstrated experimentally. Furthermore, due to the weak van der Waal (vdW) forces between the 2D material layers, the electrostatic environment of single top gate device diverges from the usual ultra-thin materials. Therefore, in this work, using BP as the example, we firstly investigate the device performance of few-layer 2D layered material FETs with a single top gate device structure MOSFET and Schottky barrier FET. The current characteristics of the devices is obtained via a non-equilibrium Green’s function (NEGF) quantum simulator using Wannier function Hamiltonians based on first principle calculations, which enables the investigation of the individual BP layers potential profile at different gate biases. Therefore, the effect of van der Waals interlayer interaction on device performance and carrier transport properties in multilayer BP FETs can be fully and properly studied. Finally, we will discuss the ultimate voltage scalability of a double-gate ultra-thin body (DG-UTB) FETs employing materials from group IV, III-V, and 2-dimensional (2D) materials, including BP, MoS2, etc., based on International Technology Roadmap for Semiconductors (ITRS) projected specifications for high performance (HP) and low power (LP) technologies. The ballistic performance of FETs designed based on the ITRS specifications for 2018 and beyond was evaluated via the semiclassical ballistic transport model. The device performance of 2D layer materials in FET applications will be compared to devices based the conversional semiconductor materials, such as Si, Ge, InGaAs and GaSb, based on ITRS roadmap requirement and their potential applications fitted into the future needed will be also addressed to provide the guidelines for future industrial development.

Effect of high-k dielectric and ionic liquid gate on nanolayer black-phosphorus field effect transistors

Nanolayer black phosphorus (BP) is a direct bandgap semiconducting two dimensional crystal, showing immense promise for future nanoelectronic devices. Here, we report the effect of high-k dielectric and ionic-liquid gate in BP field effect transistors (BP FET). An ambipolar behavior is observed in pristine BP FETs with current modulation of 104. With a high-k HfO2 encapsulation, we observed identical switching performance in the BP FETs, however, with noticeable enhancement in mobility at room temperature. In comparison to the pristine device, the HfO2 encapsulation showed a contrasting decrease in mobility at lower temperatures. BP FETs with electric double layer ionic liquid gate showed a drastic improvement in the subthreshold swing (SS) to 173 mV/dec and operation voltages less than 0.5 V in comparison to solid state SiO2 back gated devices. Our results elucidate the effect of different electrostatic conditions on BP transistor channels and open up ways for further exploration of their prospects for nanoelectronic devices and circuits.

Effective passivation of exfoliated black phosphorus transistors against ambient degradation.

Unencapsulated, exfoliated black phosphorus (BP) flakes are found to chemically degrade upon exposure to ambient conditions. Atomic force microscopy, electrostatic force microscopy, transmission electron microscopy, X-ray photoelectron spectroscopy, and Fourier transform infrared spectroscopy are employed to characterize the structure and chemistry of the degradation process, suggesting that O2 saturated H2O irreversibly reacts with BP to form oxidized phosphorus species. This interpretation is further supported by the observation that BP degradation occurs more rapidly on hydrophobic octadecyltrichlorosilane self-assembled monolayers and on H-Si(111) versus hydrophilic SiO2. For unencapsulated BP field-effect transistors, the ambient degradation causes large increases in threshold voltage after 6 h in ambient, followed by a ∼ 10(3) decrease in FET current on/off ratio and mobility after 48 h. Atomic layer deposited AlOx overlayers effectively suppress ambient degradation, allowing encapsulated BP FETs to maintain high on/off ratios of ∼ 10(3) and mobilities of ∼ 100 cm(2) V(-1) s(-1) for over 2 weeks in ambient conditions. This work shows that the ambient degradation of BP can be managed effectively when the flakes are sufficiently passivated. In turn, our strategy for enhancing BP environmental stability will accelerate efforts to implement BP in electronic and optoelectronic applications.