Bit Rate Degradation Research Articles

FAURAS: A Proxy-Based Framework for Ensuring the Fairness of Adaptive Video Streaming over HTTP/2 Server Push

HTTP/2 video streaming has gotten a lot of attention in the development of multimedia technologies over the last few years. In HTTP/2, the server push mechanism allows the server to deliver more video segments to the client within a single request in order to deal with the requests explosion problem. As a result, recent research efforts have been focusing on utilizing such a feature to enhance the streaming experience while reducing the request-related overhead. However, current works only optimize the performance of a single client, without necessary concerns of possible influences on other clients in the same network. When multiple streaming clients compete for a shared bandwidth in HTTP/1.1, they are likely to suffer from unfairness, which is defined as the inequality in their bitrate selections. For HTTP/1.1, existing works have proven that the network-assisted solutions are effective in solving the unfairness problem. However, the feasibility of utilizing such an approach for the HTTP/2 server push has not been investigated. Therefore, in this paper, a novel proxy-based framework is proposed to overcome the unfairness problem in adaptive streaming over HTTP/2 with the server push. Experimental results confirm the outperformance of the proposed framework in ensuring the fairness, assisting the clients with avoiding rebuffering events and lowering bitrate degradation amplitude, while maintaining the mechanism of the server push feature.

Content-Aware Fast Motion Estimation Algorithm for IoT Based Multimedia Service

Various applications based on IoT real-time multimedia are under the spotlight. To implement real-time multimedia service, motion estimation in video compression service has a high computational complexity. In this paper, an efficient motion search method based on content awareness is proposed consisting of three steps. The first step is motion classification using the center position cost distribution. The second step is calculation of a predictor based motion classification. The third step is setting the arm size of the search pattern based on adaptive use of the distance between the predictor and the center position. Experimental results show that the proposed algorithm achieves speed-up factors of up to 48.57% and 16.03%, on average, with good bitrate performance, compared with fast integer-pel and fractional-pel motion estimation for H.264/AVC (UMHexagonS), and an enhanced predictive zonal search for single and multiple frame motion estimation (EPZS) methods using JM 18.5, respectively. In addition, the proposed algorithm achieves a speed-up factor of up to 42.61%, on average, with negligible bitrate degradation, compared with the TZ search motion estimation algorithm for the multiview video coding (TZS) method on HM 10.0.

Measurement and verification of the impact of electromagnetic interference from household appliances on digital subscriber loop systems

We propose a verification method to assess the impact of electromagnetic interference (EMI) from household appliances on multicarrier, fixed quality, variable bit rate asymmetric digital subscriber line (ADSL) systems. Measurements of the interference waveforms from selected appliances and evaluation of their amplitude probability distributions (APDs) were made over the ADSL1 spectrum. Statistical fitting analysis on the APDs revealed that these interferences are well modelled by non-Gaussian α-stable distributions. A computer simulation program for ADSL1 transceivers was developed to estimate the achievable bit rate over standardised loops affected by these interferences. The strength of the simulated α-stable noise was calibrated through actual measurements of the coupled EMI using a cable qualifier. It was observed that a co-located household appliance can increase the noise floor on the twisted pair by several dBs. Simulation results and real-time measurements using an Internet speedometer showed that the bit-rate degradations vary widely depending on the types of appliances and could be as high as 25%. The results obtained quantify and reinforce the conclusion that the current unshielded ADSL1 infrastructure is susceptible to EMI threats from certain household appliances. The proposed verification methodology can be readily adapted to other DSL systems affected by EMI.

SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus

In this paper, a variation-tolerant low-power source-synchronous multicycle bus (SSMCB) interconnect scheme is proposed. This scheme is scalable and suitable for transferring data across different clock domains such as those in many-core SoCs and in 3-D ICs. SSMCB replaces intermediate flip-flops by a source-synchronous synchronization scheme. Removing the intermediate flip-flops in the SSMCB scheme enables better averaging of delay variations across the whole interconnect, which reduces bit-rate degradation due to within-die process variations. Monte Carlo circuit simulations show that SSMCB eliminates 90% of the variation-induced performance degradation in a six-cycle 9-mm-long 16-bit conventional bus. The proposed multicycle bus scheme also leads to significant energy savings due to the elimination of power-hungry flip-flops and the efficient design of the source synchronization overhead. Moreover, eliminating the intermediate flip-flops avoids the timing overhead of the setup time, the flip-flop delay, and the single-cycle clock jitter. This delay slack can then be translated into further energy savings by downsizing the repeaters. The significant delay jitter due to capacitive coupling has been addressed, and solutions are put forward to alleviate it. Circuit simulations in a 65-nm process environment indicate that energy savings up to 20% are achievable for a six-cycle 9-mm-long 16-bit bus.

Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme

A variation-tolerant low-power source-synchronous multicycle (SSMC ) interconnect scheme is proposed. This scheme is scalable and suitable for transferring data across different clock domains such as those in “many-core” SoCs and in 3D-ICs. SSMC replaces intermediate flip-flops by a source-synchronous synchronization scheme. Removing the intermediate flip-flops in the SSMC scheme enables better averaging of delay variations across the whole interconnect, which reduces bit-rate degradation due to within-die WID process variations. Monte Carlo circuit simulations show that SSMC eliminates 90% of the variation-induced performance degradation in a 6-cycle 9 mm-long 16-bit conventional bus. The proposed multicycle bus scheme also leads to significant energy savings due to eliminating the power-hungry flip-flops and efficiently designing the source synchronization overhead. Moreover, eliminating intermediate flip-flops avoids the timing overhead of the setup time, the flip-flop delay, and the single-cycle clock jitter. This delay slack can then be translated into further energy savings by downsizing the repeaters. The significant delay jitter due to capacitive coupling has been addressed and solutions are put forward to alleviate it. Circuit simulations in a 65-nm process environment indicate that energy savings up to 20% are achievable for a 6-cycle 9 mm long 16-bit bus.

Analysis and Design of Timing Recovery Schemes for DMT Systems over Indoor Power-Line Channels

Discrete multitone (DMT) modulation is a suitable technique to cope with main impairments of broadband indoor power-line channels: spectral selectivity and cyclic time variations. Due to the high-density constellations employed to achieve the required bit-rates, synchronization issues became an important concern in these scenarios. This paper analyzes the performance of a conventional DMT timing recovery scheme designed for linear time-invariant (LTI) channels when employed over indoor power lines. The influence of the channel cyclic short-term variations and the sampling jitter on the system performance is assessed. Bit-rate degradation due to timing errors is evaluated in a set of measured channels. It is shown that this synchronization mechanism limits the system performance in many residential channels. Two improvements are proposed to avoid this end: a new phase error estimator that takes into account the short-term changes in the channel response, and the introduction of notch filters in the timing recovery loop. Simulations confirm that the new scheme eliminates the bit-rate loss in most situations.