Bitline Leakage Current Research Articles

Bit-line leakage current tracking and self-compensation circuit for SRAM reliability design

For low voltage CMOS static random access memory (SRAM) cells, the leakage current on bit-lines will slow down the reading operation and even lead to error reading. Herein we report a 4B4C circuit composed of 8T SRAM arrays, four bit-lines and four coupling capacitors to track and compensate the bit-line leakage current (BLLC). The assistant bit-lines are used to control the connection of capacitors. The coupling capacitors are used to compensate voltage losses caused by the BLLC, and improve the maximum tolerable current from primary bit-line. The timing diagram and output waveforms verify the compensatory effects of coupling capacitors. The 4B4C circuit shows fast reading operation and increases the maximum tolerable leakage current to 17.8 times compared with conventional circuit at FS process corner. The 4B4C circuit can keep 100% correct reading till 200 μA from Monte Carlo simulations. The 4B4C circuit enhances SRAM reading reliability and shows huge potential in very-large scale memory arrays.

Stable Local Bit-Line 6 T SRAM Architecture Design for Low-Voltage Operation and Access Enhancement

To incur the memory interface and faster access of static RAM for near-threshold operation, a stable local bit-line static random-access memory (SRAM) architecture has been proposed along with the low-voltage pre-charged and negative local bit-line (NLBL) scheme. In addition to the low-voltage pre-charged and NLBL scheme being operated by the write bit-line column to work out for the write half-select condition. The proposed local bit-line SRAM design reduces variations and enhances the read stability, the write capacity, prevents the bit-line leakage current, and the designed pre-charged circuit has achieved an optimal pre-charge voltage during the near-threshold operation. Compared to the conventional 6 T SRAM design, the optimal pre-charge voltage has been improved up to 15% for the read static noise margin (RSNM) and the write delay enriched up to 22% for the proposed NLBL SRAM design which is energy-efficient. At 400 mV supply voltage and 25 MHz operating frequency, the read and write energy consumption is 0.22 pJ and 0.23 pJ respectively. After comparing with the related works, the access average energy (AAE) is lower than in other works. The overall performance for the proposed local bit-line SRAM has achieved the highest figure of merit (FoM). The designed architecture has been implemented based on the 1-Kb SRAM macros and TSMC−40 nm GP process technology.

Self‐compared bit‐line pairs for eliminating effects of leakage current

This Letter proposes a new scheme to eliminate the bit-line leakage current of static random access memory. The proposed scheme utilises a four-input sense amplifier to amplify the voltages of self-compared bit-line pairs. The bit-lines of the proposed structure have no series capacitances and are directly connected to the sense amplifier input. By this way, read delay and error caused by the leakage current of bit-lines will be eliminated. Simulation results in SMIC 28 nm CMOS process design kits show that the proposed scheme has better stability and can decrease delay time by 41.1% at 0.9 V supply voltage compared with the X-Calibration technology.

Design of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement

This paper presents a 9T multi-threshold (MTCMOS) SRAM macro with equalized bitline leakage and a content-addressable-memory-assisted (CAM-assisted) write performance boosting technique for energy efficiency improvement. A 3T-based read port is proposed to equalize read bitline (RBL) leakage and to improve RBL sensing margin by eliminating data-dependence on bitline leakage current. A miniature CAM-assisted circuit is integrated to conceal the slow data development with HVT devices after data flipping in write operation and therefore enhance the write performance for energy efficiency. A 16 kb SRAM test chip is fabricated in 65 nm CMOS technology. The operating voltage of the test chip is scalable from 1.2 V down to 0.26 V with the read access time from 6 ns to 0.85 $\mu {\rm s}$ . Minimum energy of 2.07 pJ is achieved at 0.4 V with 40.3% improvement compared to the SRAM without the aid of the CAM. Energy efficiency is enhanced by 29.4% between 0.38 V $\sim$ 0.6 V by the proposed CAM-assisted circuit.

A 130 mV SRAM With Expanded Write and Read Margins for Subthreshold Applications

SRAM suffers read-disturb and write failures at a low supply voltage, especially at deep subthreshold operation. This study proposes a 9T-SRAM cell with a data-aware-feedback-cutoff (DAFC) scheme to enlarge the write margin and dynamic-read-decoupled (DRD) scheme to prevent read-disturb for achieving deep subthreshold operation. A 30 mV negative-pumped wordline scheme is employed to suppress bitline leakage current. The fabricated 90 nm 32 Kb 9T-SRAM macro achieves 130 mV VDDmin. All the 32 Kb 9T cells are stable across read and write operations when operated at 105 mV.

Noise-Immune Embedded NAND-ROM Using a Dynamic Split Source-Line Scheme for VDDmin and Speed Improvements

Embedded NAND-type read-only-memory (NAND-ROM) provides large-capacity, high-reliability, on-chip non-volatile storage. However, NAND-ROM suffers from code-dependent read noises and cannot survive at low supply voltages (VDDs). These code-dependent read noises are primarily due to the charge-sharing effect, bitline leakage current, and crosstalk between bitlines, which become worse at lower VDD. This study proposes a dynamic split source-line (DSSL) scheme for NAND-ROM. The proposed scheme overcomes code-dependent read noises while improving the read access time and suppressing the active-mode gate leakage current, with only a 1% area penalty in the cell array. Experiments on a fabricated 256 Kb macro using a 90 nm industrial logic process demonstrate that the proposed DSSL scheme achieves 100% code-pattern coverage under a small sensing margin. Additionally, the DSSL NAND-ROM works with a wide range of supply voltages (1-0.31 V) with a 38%, 45.8%, and 37% improvement in speed, power, and standby current, respectively, at VDD = 1 V.

A Voltage Scalable 0.26 V, 64 kb 8T SRAM With V$_{\min}$ Lowering Techniques and Deep Sleep Mode

A voltage scalable 0.26 V, 64 kb 8T SRAM with 512 cells per bitline is implemented in a 130 nm CMOS process. Utilization of the reverse short channel effect in a SRAM cell design improves cell write margin and read performance without the aid of peripheral circuits. A marginal bitline leakage compensation (MBLC) scheme compensates for the bitline leakage current which becomes comparable to a read current at subthreshold supply voltages. The MBLC allows us to lower Vmin to 0.26 V and also eliminates the need for precharged read bitlines. A floating read bitline and write bitline scheme reduces the leakage power consumption. A deep sleep mode minimizes the standby leakage power consumption without compromising the hold mode cell stability. Finally, an automatic wordline pulse width control circuit tracks PVT variations and shuts off the bitline leakage current upon completion of a read operation.

X-Calibration: A Technique for Combating Excessive Bitline Leakage Current in Nanometer SRAM Designs

In an SRAM circuit, the leakage currents on the bit lines are getting increasingly prominent with the dwindling of transistors' threshold voltages as the technology scales down to 90 nm and beyond. Excessive bit-line leakage current results in slower read operations or even functional failure. In this paper, we present a new technique, called X-calibration, to combat this phenomenon. Unlike the previous method that attempts to compensate the leakage current directly, this scheme first transforms the bit-line leakage current into an equilibrium offset voltage across the bit-line pair, and then simple circuitry is utilized to cancel this offset accurately at the input of the sense amplifier so that the sensing is not affected by the bit-line leakage. SPICE simulation of a 1 Kbit SRAM macro shows that this X-calibration scheme can handle 83% higher bit-line leakage current than the previous bit-line leakage compensation scheme. Measurement results of the test chip show that the SRAM macro adopting X-calibration scheme can cope with up to 320 muA bit-line leakage current.

Low-Voltage and Low-Current Flash Memory Using Source Induced Band-to-Band Tunneling Hot Electron Injection to Perform Programming

A novel n-channel flash memory cell, which uses source induced band-to-band hot electron injection (SIBE) to perform programming, is proposed in this paper. With the proposed programming method, the drain voltage and the control gate voltage can be reduced to as low as -3.6 V and 10 V with the assistance of the source voltage, and the programming speed can increase up to 10 µs. Moreover, the programming current is reduced to approximately 3.0 µA, and a large read current of 64 µA is also realized. The simulation and the testing results show that the proposed flash cell features low programming voltage, low power, high programming efficiency, high read current, low bit-line leakage current, and good reliability.

A bitline leakage compensation scheme for low-voltage SRAMs

A bitline leakage current of an SRAM, induced by leakage current of the transmission transistors in the cells that are associated with the bitline, increases as the threshold voltage (V/sub TH/) of the transistors is reduced for high performance at low power-supply voltage (V/sub DD/). The increased bitline leakage causes slow or incorrect read/write operation of an SRAM because the leakage current acts as noise current for a sense amplifier. In this paper, the problem has been solved from a circuitry point of view, and the scheme which detects the bitline leakage current in a precharge cycle and compensates for it during a read/write cycle is proposed. Employing this scheme, the SRAM with 360-/spl mu/A bitline leakage current can perform a read/write operation at the same speed as one that has no bitline leakage current. This enables a 0.1-V reduction in V/sub TH/, and keeps the V/sub TH/ and delay scalability of a high-performance SRAM in technology progress. An experimental 8-Kb SRAM with 256 rows is fabricated in a 0.25-/spl mu/m CMOS technology, which demonstrates the effectiveness of the scheme.