Bit-slice Research Articles

Design of Bit Slice Processor based on Reconfigurable Approximate Carry Look-Ahead Adder

A highly efficient approximate addition plays a vital role in arithmetic operations. A special addition mechanism employed in the proposed work consists of both exact and approximate modes of operation suitable for both error tolerant and exact applications. The proposed adder is more area and power efficient compared with other conventional approximate carry look-ahead adders. It is constructed by splitting the input into two parts namely, approximate part and augmenting part. If both produce carry it will be exact output, while the carry produced by approximate part will be imprecise. Based on this mechanism an efficient reconfigurable carry look-ahead adder is designed and applied to a bit-slice processor. Bit slicing is technique to construct a processor by using n-bit CPU. The error rate is also minimized in the proposed technique by 10% compared to existing designs. Compared with conventional approximate adder, the proposed reconfigurable approximate adder produce better results in terms of area and power

Symmetric SPN block cipher with Bit Slice involution S-box

Feistel and SPN are the two main structures in a block cipher. Feistel is a symmetric structure which has the same structure in encryption and decryption, but SPN is not a symmetric structure. Encrypt round function and decrypt round function in SPN structure have three parts, round key addition and substitution layer with S-box for confusion and permutation layer for defusion. Most SPN structure for example ARIA and AES uses 8 bit S-Box at substitution layer, which is vulnerable to Square attack, Boomerang attack, Impossible differentials cryptanalysis etc. In this paper, we propose a SPN which has a symmetric structure in encryption and decryption. The whole operations of proposed algorithm are composed of the even numbers of N rounds where the first half of them, 1 to N/2 round, applies a right function and the last half of them, (N+1)/2 to N round, employs an inverse function. And a symmetry layer is located in between the right function layer and the inverse function layer. The symmetric layer is composed with a multiple simple bit slice involution S-Boxes. The bit slice involution S-Box symmetric layer increases difficult to attack cipher by Square attack, Boomerang attack, Impossible differentials cryptanalysis etc. The proposed symmetric SPN block cipher with bit slice involution S-Box is believed to construct a safe and efficient cipher in Smart Card and RFID environments where electronic chips are built in.

An Algebraic Approach to Formal Verification of Microprocessors

In this letter we report the formal verification of microprocessors. After we describe algebraically a bit-sliced microprocessor at both function and logic levels, we apply the symbolic manipulation of Mathematica.

Analysis of single-event effects in combinational logic-simulation of the AM2901 bitslice processor

Using SEUTool (a synthesized VHDL based simulator of single-event fault propagation in combinational circuitry), we have performed a single-event study on a custom-designed CMOS AM2901, a 4-bit bit-slice processor. Analysis shows interesting general trends for single-event upset effects in complex combinational/sequential circuits.

A high-speed public key encryption processor

A 0.5-μm design rule single-chip public key encryption processor is described and evaluated. This full-custom chip employs the high-speed redundant binary method. A bit-slice processor macro is used as the arithmetic unit. The processor is capable of executing 1024-bit operations in as little as 50 ms. The three main features of this chip are: 1) keys of arbitrary length up to 1024 bits can be used, 2) the data length can be read before the output of the computation result, and 3) for safe handling of RSA cryptosystem private keys, the private key is stored in a register on the chip that cannot be read out. Ordinary personal computers equipped with an expansion board that employs this chip are capable of performing at high speed. The chip can also be mounted on a PC Card [1] by using a TQFP, allowing implementation as a portable personal device. Through the use of such PC boards or cards, this chip promises to play an important role in safer real-time electronic commerce over the Internet in the near future. © 1998 Scripta Technica. Syst Comp Jpn, 29(1): 20–32, 1998

MEMPHIS 2000-a modular experiment multiparameter pulse height instrumentation system

For the data acquisition in nuclear physics experiments with multidetector arrays like OSIRIS, the MEMPHIS 2000 system has been developed. The important features are the compact mechanics, the galvanic decoupling of the sensitive analog part from the host computer power supplies, and simple interfacing with existing computer hardware and ADCs. The use of bit-slice processors provides software control of the setup and the configuration of the whole system. The one-crate version consists of 28 high-resolution (16-b) input channels for NIM-ADCs (Silena Type 7420/G, 7411), two bit-slice processors for ADC control, and three microprocessors for software download, data transfer, and setup. Online acquisition, recording, and analysis of experimental data as well as experiment control are implemented on the VAX-Station.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A fine-grain architecture for relational database aggregation operations

The design and simulation of a bit-sliced processor for relational database aggregation functions, are discussed. The processor, which addresses an important, computationally expensive problem in database computers, takes two tuples as input (one bit at a time) and returns two bits as output every clock cycle. A larger aggregation unit uses a number of identical slice processors, connected according to odd-even network topology, to achieve improved performance on a parallel pipelined processor. The data processing time is completely overlapped with the input and output of data to and from the unit. The design is independent of the tuple size, and since a bit-serial computation is used, the system requires limited interconnection.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Universal logic implementer: a general purpose tool for a digital logic design laboratory

The authors present a general-purpose digital logic implementer, a tool designed to serve as a workstation for laboratory experiments in the digital logic and computer architecture courses taught in the Electrical and Computer Engineering Department at Washington State University. The logic implementer is a versatile tool suitable for a wide spectrum of experiments, from simple gate-level implementation of logic circuits to the implementation of microprogrammed bit-slice processors. The basic features of the logic implementer include generality of applications, easy-to-use environment, and robust, reliable interconnections.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Universal logic implementer: a general purpose tool for a digital logic design laboratory

The authors present a general purpose digital logic implementer, a tool designed to serve as a workstation for laboratory experiments in the digital logic and computer architecture courses taught in the Department of Electrical and Computer Engineering at Washington State University. The logic implementer is a versatile tool suitable for a wide spectrum of experiments, from simple gate-level implementation of logic circuits to the implementation of microprogrammed bit-slice processors. The basic features of the logic implementer include generality of applications, easy-to-use environment, and robust, reliable interconnections. >

CMOS/SOI hardening at 100 Mrad (SiO/sub 2/)

Hardened CMOS silicon-on-insulator (SOI) 29101 microprocessor elementary cells and transistors were irradiated at levels between 10 Mrad(SiO/sub 2/) and 1 Grad(SiO/sub 2/) (/sup 60/Co and 10-keV X-rays). SIMOX buried oxide behavior in the range of 100 Mrad(SiO/sub 2/) and a channel-stopped MOS/SOI structure avoiding lateral leakage current are presented. These two items indicate the feasibility of a CMOS/SOI technology operating in the hundred Mrad(SiO/sub 2/) range. The SOI structure is described. The total dose radiation effects for /sup 60/Co gamma rays and 10-keV X-rays are discussed. Accelerated buried oxide recovery is studied. Irradiation results of a bit-slice microprocessor test chip and elementary cell are presented. >

A general real-time decoder based on amd2900 devices

A bit-slice microprocessor-based real-time decoder has been proposed in this paper. A microprocessor-based architecture is preferable because of its programability, availability, low cost and simplicity of design. Two strategies are adapted to increase throughput of the decoder for real-time decoding. First, bit-slice microprocessors are used and alu word length is chosen to be equal to that of a code word. Second, decoding operation is accomplished in two steps, namely (1) Error detection and (2) Error correction. It takes relatively much longer time to correct errors. Therefore, a buffer memory is used to store incoming blocks as more than one block may be received during a decoding cycle. The design is versatile since different decoding algorithms can be executed by changing the microprogram. Minor, apparent and simple changes have to be made in the design to decode codes of longer block length.

A 150-MOPS GaAs 8-bit slice processor

The architecture, circuit design, and test results for a GaAs 8-b slice processor IC are presented. The device is a high-speed cascadable element intended for use in MIL-STD-1750A computers, reduced-instruction-set computer (RISC) systems, signal processors, and numerous other applications where high speed and radiation hardness are required. The bus-oriented architecture features a 31-word*8-b two-port register file, a fast eight-function ALU, an 8-bit address port an 8-b bidirectional data port, and associated shifting, decoding, and multiplexing functions. Ancillary logic commonly mechanized in external hardware has been included on-chip. The 9400-transistor LSI device demonstrated peak performance above 150 million operations per second (MOPS) at 9.2 W; a lower power version executes 100 MOPS at 4.2 W.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Application of a microprogrammable microprocessor in digital signal processing analysis

In this paper, a digital signal processing system based on a microprogrammable bit-slice microprocessor is described. A horizontal microinstruction format with a field width of 124 pipelined bits is used. Hardware is designed to implement the Fourier analysis, linear prediction code, and other mathematical equations often involved in digital signal processing. The system is shown to be practical and flexible in student laboratory environment and research.

8 -BIT Microcomputer for Laboratory Purposes using I 3000 Microprocessor Family

Thh design of microcomputer proposed here is based on the microprocessor chips of Intel 3000 family. The idea of developing such a microcomputer finds its utility in the use of microprocessors and microcomputers for laboratory purposes.The microcomputer facilitates the user to exploit all the constituent units of the microcomputer separately and as well as to operate with the system as a whole. System provides the advantage to operate separately with Central Processing Unit (13002), Control Unit (I 3001) and Priority Interrupt Control Unit (8214). The user may execute the microprogram, co-relating all the three units.The use of bit-slice processor provides flexibility to the circuit. The number of bits processed can be increased only by adding new chips (processor chips). There is a built in Random Access Memory with a capacity of 1 k bytes, which is enough to store a micro-program.

Concurrently totally self-checking microprogram control unit with duplication of microprogram sequencer

This paper presents a new design method for concurrently Totally Self-Checking Microprogram Control Units of bit-slice microprocessors. We consider a fault model that includes arbitrary failures in a single IC package and multiple errors on address, data and control buses. In our method the microprogram sequencer and the remaining functional units that support it are duplicated. Also, the microinstructions with their b-bit addresses are encoded in a distance-2 n-adjacent encoding scheme. Finally an N-adjacent code checker is employed to monitor the outputs from the microprogram memory and the microprogram sequencer. The checker and hence the whole Microprogram Control Unit becomes concurrently Totally Self-Checking by using a small number of microinstructions stored in predefined addresses in the microprogram memory. Our method in comparison to others has the added advantage to detect concurrently not only the permanent faults, but also temporary faults occurring during normal operation.

The Texas Instruments TMS320C25 Digital Signal Microcomputer

Capable of 10 million operations per second, the newest member of the TMS320 family can serve as an inexpensive alternative to bit-slice processors or custom ICs in digital signal processing applications.

The dynamically reconfigurable CAP Array Chip I

Array Chip I is a bit-slice processor chip using novel fault-tolerant, large-area integration techniques. It provides 20 1-bit bit-slice processors, or cells, which are controlled from a single microinstruction stream. The chip is implemented in 3-/spl mu/m double-metal n-well CMOS, has 115000 transistors, and an unusually large die size of 500/spl times/650 mil. Prototype yields, with at least 16 cells operational exceed 25%. The chip configuration is controlled by software at run time to form bit-parallel or bit-serial words of arbitrary size and to exclude defective elements. Following system initialization, defective elements are invisible at both the programming and the physical chip interconnect levels. Thirty-six of these chips have been used in a prototype cellular-array parallel processor employing the single-instruction stream, multiple-data stream (SIMD) architecture.

Digital Distance Relay mho Elements Using Bit-Slice Technology

Distance relays are a common method of protecting power transmission lines. This paper deals with a digital method for implementing mho elements of a distance relay. The method is based on calculation of an apparent impedance which is compared to a fixed circular characteristic. Digital mho elements have been designed and implemented using a bit-slice microprocessor and a fast array multiplier. Samples of voltage and current for a three-phase system are taken 16 times per cycle at a power line frequency of 60 Hz. The system contains a total of 12 mho elements for six phase-ground and six phase-phase loops.

An interactive diagnostic/debugging subsystem for bit-slice processors

This paper discusses the design and implementation of a debugging/diagnostic subsystem for a bit-slice processor. The subsystem uses serial shadow registers under the control of a single chip microcomputer both to observe and to control processor behavior. Serial lines link the microcomputer to a diagnostic host which provides the user with a comprehensive set of interactive diagnostic commands. Using these commands, the user is able to load the writable control store, verify its contents, load mapping facilities, set breakpoints and examine registers during single-stepping sequences. The subsystem can considerably speed up the firmware development process and when incorporated into the design as a permanent feature, it provides a very low-cost facility for register-level diagnostics during the life of the system. Portability of the diagnostic subsystem across a number of processors is also possible and is conducive to the efficient management of machine diagnosis in the field.

Procedure for testing a bit-sliced microprocessor

A procedure for testing a multiplexer is proposed, It uses 1-out-of-k code and its inverse (2k - 1) modulo residue. The concept is further extended to the 1-bit cell model of a bit-slice processor described by Sridhar and Hayes in 1981. It is shown that the proposed method results in a smaller overall test size than that reported by Sridhar and Hayes.