Bipolar/BiCMOS Circuits And Technology Meeting Research Articles

Threading Dislocation Reduction of Ge by Introducing a SiGe/Ge Superlattice

Ge growth on Si is essential e.g. for photonics device integration (e.g. Ge photodiode) into Si based CMOS platform (1). However, due to 4.2% of lattice mismatch between Ge and Si, misfit dislocations (MD) and threading dislocations (TD) are introduced for strain relaxation after exceeding critical thickness. In order to realize low-darkcurrent Ge photodiode, improvement of crystallinity is important. High quality Ge growth techniques by combining various annealing techniques (at 800~850oC) are reported (2-3). However, because of low melting point of Ge (937oC), the Ge growth process is typically integrated at the last part of front-end process. Therefore, these annealing processes are affecting device parameters of existing devices. In previous paper, we reported Ge/SiGe superlattice (SL) fabrication and found improvement of TD density (TDD) by increasing Si composition of SiGe in the SL (4). Here we report TDD improvement of Ge by introducing the SL without annealing.Ge growth with SiGe/Ge SL is carried out using reduced pressure chemical vapor deposition system. Si(100) wafers are used. After an HF last cleaning, the wafer is loaded into reactor and baked at 1000oC and cooled down to 600oC in H2 and further cooled down to 350oC in N2. After that 100 nm-thick seed Ge is deposited using N2-GeH4 gas. Then the wafer is heated up to 500oC in H2 and Ge/SiGe superlattice is fabricated using H2-GeH4 and H2-SiH4-GeH4 gases, respectively. Furthermore, 2.8 µm thick Ge is deposited at 550oC using H2-GeH4 gas.Thickness is measured by cross section SEM and spectroscopic ellipsometry. TDD is determined by Secco defect etching technique. Strain and relaxation of Ge and SiGe layers are measured by XRD reciprocal space mapping. Distribution of the MD and the TD are measured by cross section TEM.In the case of direct Ge growth on Si (Fig. 1a), MDs are formed at interface between Ge and Si. TDs are spreading into the Ge layer. Some of the TDs are long and extending to surface. These MD and TD formations are due to the lattice mismatch between Ge and Si. On the other hand, in the case of Ge sample grown on ×20 Si0.3Ge0.7 / Ge SL (Fig. 1b), most of MDs are formed at interface between 100 nm-thick Ge buffer and Si substrate. Additionally high density of TDs are observed in the Ge buffer and the SL layer. In the SL layer, lower TDD is observed in the upper part compared to that in the deeper part. At the interface between upper 2.8 µm thick Ge and the SL layer, MD and high density of TDs toward lateral direction is observed indicating relaxation. TDD in the 2.8 µm thick Ge layer seems to be lower compared to that in Fig. 1a).In the case of direct Ge growth on Si, TDD of ~7.5×108 cm-2 is obtained (Fig. 2). The TDD is comparable to previously reported results (2). By depositing 2.8 µm thick Ge on Si0.2Ge0.8 SL, TDD is decreased to ~5.4×108 cm-2. With decreasing Ge concentration of SiGe layer of the SL, decrease of TDD is observed until 40%. However, by replacing SiGe layers to mono-layers of Si, increased TDD is observed, which might be due to too high strain at interface between Si and SiGe.Figure 3 shows TDD of 2.8 µm thick Ge deposited on Si0.2Ge0.8/Ge SL with different Si0.2Ge0.8 and Ge thickness combination without changing periodicity of the SL. Lower TDD is observed when the 2.8 µm thick Ge is deposited on the SL with higher Si0.2Ge0.8 thickness. Possible reason is higher degree of relaxation of the SL layer.In Fig. 4, TDD of 2.8 µm thick Ge deposited on SLs of various lattice parameters are shown. By reducing lateral lattice parameter of the SiGe/Ge SL by increasing SiGe thickness or Si concentration, TDD decreases. The reduction of the TDD is fitting to one line for both cases. These results indicate that higher plastic relaxation of the SL occurs on the Ge buffer due to increased compressive strain of SiGe in the SL, and the TDD reduction of the Ge on the SL may be caused by similar mechanism of reverse graded buffer. By introducing SiGe/Ge SL, multiple effect of the reverse graded buffer may be expected. Reference (1) S. Lischke et al. Proc. IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) , (2014) 29(2) Y. Yamamoto et al Solid-State Electron. 60 (2011) 2(3) Y. Yamamoto et al. Semicond. Sci. Technol. 33 (2018) 124007(4) Y. Yamamoto et al. Jpn. J. Appl. Phys. 59, SGGK10 (2020) Figure 1

(Invited) Integration of an Epitaxial-Base-Link HBT Device with fT = 300GHz, fmax 480GHz in 90nm CMOS

SiGe HBT based BiCMOS technologies have found widespread use in millimeter-Wave (mmW) applications such as high-speed communication and automotive radar, but are also receiving increased attention for operating frequencies above 100GHz. The drive for higher operating frequencies while reducing power consumption continues to fuel the development of new BiCMOS technologies with HBTs featuring higher switching speeds (fmax) integrated with smaller, more power efficient and cost effective CMOS nodes. There is strong evidence however, that in volume production double poly self-aligned (DPSA) HBT architectures may be limited to fmax of 400GHz[i],[ii],[iii],[iv],[v],[vi]. Alternative HBT architectures to overcome this limitation have been proposed[vii],[viii],[ix].In this paper we report the successful integration of a SiGe HBT module with fT = 300GHz, fmax = 480GHz in a 90nm BiCMOS technology platform. Building on previous studies by IHP[x] and Infineon[xi] the Epitaxial-Base-Link process flow was further adapted for compatibility to the 90nm CMOS base technology. The new technology platform features seven Cu metal layers high quality passives including a TaN resistor and a MiM capacitor positioned between metal levels 6 and 7 for low parasitic substrate coupling. One metal layer was added compared to the 130nm platform to facilitate the transition from thin wire to RF metallization.Figure 1 shows a TEM cross section of one of the first successful 90nm BiCMOS runs. Key challenges of the integration into the new CMOS node will be summarized in the presentation. The same device showed nearly ideal Gummel characteristics. CML ring oscillators with a design width EW of 190nm and 2.8 µm length achieved a wafer mean gate delay of 1.86ps with a standard deviation of 1.9%.Acknowledgment: This work was supported by the European Commission and the German Federal Ministry of Education and Research (BMBF) under project ref# 16ESE0202S ECSEL-TARANTO. [i] V. P. Trivedi et al., “A 90nm BiCMOS Technology featuring 400 GHz fMAX SiGe:C HBT”, in Bipolar / BiCMOS Circuits and Technology Meeting, 2016, pp. 60-63. [ii] V. Jain et al., “Device and circuit performance of SiGe HBTs in 130nm BiCMOS process with fT/fmax of 250/330GHz,” IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2014, pp. 96-99. [iii] P. Chevalier et al., “A 55 nm triple gate oxide 9 metal layers SiGe BiCMOS technology featuring 320 GHz fT / 370 GHz fMAX HBT and high-Q millimeter-wave passives,” in International Electron Devices Meeting (IEDM), 2014, pp. 3.9.1-3.9.3. [iv] J. Pekarik et al., “A 90nm SiGe BiCMOS technology for mm-wave and high-performance analog applications,” in IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2014, pp. 92–95. [v] P. Hurwitz, R. Kanawati, K. Moen, E. Preisler, S. Chaudhry and M. Racanelli, "Advances in RF foundry technology for wireless and wireline communications," 2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), Austin, TX, 2016, pp. 5-8. [vi] J. Böck et al., “SiGe HBT and BiCMOS process integration optimization within the DOTSEVEN project”, in Bipolar / BiCMOS Circuits and Technology Meeting, 2015, pp. 121-124. [vii] Q. Z. Liu et al, “SiGe HBTs in 90nm BiCMOS Technology demonstrating fT / fmax 285GHz / 475GHz through simultaneous reduction of base resistance and extrinsic collector capacitance”, ECS transactions, 64(6) , 2014, pp. 285 – 294. [viii] A. Fox, B. Heinemann, R. Barth, S. Marschmeyer, C. Wipf and Y. Yamamoto, "SiGe:C HBT architecture with epitaxial external base," 2011 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Atlanta, GA, 2011, pp. 70-73. [ix] V.T. Vu, D. Celi, T. Zimmer, S. Fregonese, P. Chevalier, “Advanced Si/SiGe HBT architecture for 28-nm FD-SOI BiCMOS”, in Bipolar / BiCMOS Circuits and Technology Meeting, 2016, pp. 64-67. [x] B. Heinemann et al., "SiGe HBT with fx/fmax of 505 GHz/720 GHz," 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2016, pp. 3.1.1-3.1.4. [xi] D. Manger et al., "Integration of SiGe HBT with fT=305 GHz, fmax=537GHz in 130nm and 90nm CMOS," 2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), San Diego, CA, 2018, pp. 76-79. Figure 1

Introduction to the Special Section on the 2015 Bipolar/BiCMOS Circuits and Technology Meeting

This Special Section of the IEEE Journal of Solid-State Circuits includes extended papers that were presented at the 29th IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) held on October 26–28, 2015, in Boston, MA, USA.

Introduction to the Special Section on the 26th Bipolar/BiCMOS Circuits and Technology Meeting

This September Issue of the IEEEJournal of Solid-State Circuits contains a special section of four papers from the 26th Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), held on September 30 to October 3, 2012, in Portland, Oregon, USA.

Introduction to the Special Section on the 23rd Bipolar/BiCMOS Circuits and Technology Meeting

The five papers in this special section are extended papers from the 23rd Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), held October 12-14,2009, in Capri, Italy.

2010 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) 4–6 October in Austin [Conference Reports

2010 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) 4–6 October in Austin [Conference Reports

Introduction to the Special Section on the 2008 Bipolar/BiCMOS Circuits and Technology Meeting

The five papers selected and presented here were recommended for publication by the session (Co-)Chairs of the 2008 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), held in Monterey, California, USA.

Introduction to the 2006 Bipolar/BiCMOS Circuits and Technology Meeting

HIS section of the Special Issue of the IEEE JOURNAL OF SOLID-STATE CIRCUITS contains extended versions of papers solicited from presentations at the 2006 Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), held in Maastricht, The Netherlands. At the annually held BCTM, process engineers, circuit designers and CAD/modelling engineers present their latest results in a highly interactive manner. A one-day short course precedes the conference, and a workshop on Compact Modeling is held after the BCTM. The four papers presented here were recommended for publication by the session (Co-)Chairs of the conference. All papers went through the regular review process of the JOURNAL. The number of papers submitted has stabilized at around 100 over the recent years, with 106 papers submitted in 2006, of which 67 were presented in 15 technical sessions. In 2007, the conference will be held in Boston, MA. In 2008, the conference will most probably be co-located with the Compound Semiconductor IC Symposium (CSICS) in Monterey, CA. The first paper, by Nicolson et al., describes the design and realization of SiGe BiCMOS voltage-controlled oscillators (VCOs) with operating frequencies ranging from 77 to 106 GHz. Such oscillators can be used for, for example, 77-GHz automotive radar and 94-GHz imaging applications. The oscillators are based on a Colpitts architecture and are realized in two generations of SiGe technology. The 106-GHz VCO operates from a 2.5-V supply voltage and achieves a phase noise of 101.3 dBc/Hz at 1-MHz offset from the carrier. The paper also presents a comparison between MOS and HBT varactors. Differentially tuned MOS varactors are shown to provide superior performance over HBT varactors for achieving low phase noise. A further interesting aspect of this paper is that the circuits make extensive use of (square) inductors rather than transmission lines to realize the inductances, despite the low inductance values. In addition to the oscillator circuits, a differential MOS-HBT output buffer is also described that delivers an output power of 10.5 dBm at 87 GHz. Based on the scaling properties of the VCOs across the two generations of the process, the authors conclude that VCOs can be used as IC process monitor circuits. The second paper, by van Bezooijen et al., describes power amplifier protection methods based on adaptive output power control. The intended application is cellular phone power amplifiers, but the protection concept is generic. The proposed circuit and methodology provides protection against over-voltage, over-temperature, and over-current. Protection is achieved by detection of the power amplifier die temperature, collector peak voltage, and collector current, and reducing the output power control voltage if one or more of these variables

2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) in Boston, September 30 to October 2, Dr. Tak H. Ning to Deliver Keynote Address

Dr. Tak H. Ning to Deliver Keynote Address BCTM 2007 will feature keynote speaker Tak H. Ning on the "Historical Development of Devices Based on Bipolar Phenomena." The conference will offer two full days of technical papers, including a session on emerging technologies, and a short course on bipolar IC design.

2006 IEEE Bipolar/BiCMOS circuits and technology meeting (BCTM) in Maastricht, the Netherlands, 8–10 October

You want to be at the IEEE Bipolar/BiCMOS Circuits and Technology Meeting 2006 (BCTM) if you're interested in leading edge processes, devices, and circuits used in state-of-the-art telecom and power control systems. Bipolar/BiCMOS technologies, particularly SiGe HBT BiCMOS, play a key role in these systems.

Special Issue on High-Speed Circuits: 2002 Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)

Special Issue on High-Speed Circuits: 2002 Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)

Bipolar/BiCMOS circuits and technology meeting

Wireless communications is a burgeoning market area and a major driver behind the semiconductor industry, and SiGe BiCMOS and III-V technologies have emerged as the manufacturing processes of choice for many wireless ICs. If you work or are interested in this exciting area, then the IEEE Bipolar/bicmos circuits and technology meeting (BCTM) is a conference you want to attend.

The process of choice for wireless, Bipolar/BiCMOS convenes in Monterey, California

Wireless communications is a burgeoning market and a major driver behind the semiconductor industry, and SiGe BiCMOS and III-V technologies have emerged as the manufacturing processes of choice for many wireless ICs. If you work in or are interested in this exciting area, then the IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) is a conference you will want to attend, scheduled 29 September–1 October 2002.