Binding In High Level Synthesis Research Articles

Aging-aware scheduling and binding in high-level synthesis considering workload effects

Transistor aging is a major reliability concern in nanoscale digital design, and addressing it during high-level synthesis (HLS) is essential to enhance the lifetime of circuits. Motivated by exploring workload effects on aging, we propose an HLS flow that takes workload into account in binding and scheduling steps. We first construct an aging prediction model using support-vector machines (SVM)-based regression techniques. Then, scheduling is performed by utilizing a priority list, which is created based on aging of operations. By exploiting prediction models, functional unit (FU) binding and port assignment are performed simultaneously with the aim of optimizing aging, along with other objectives, by managing the workload of FUs. The results of the proposed method show that the aging rate of FUs is reduced up to 4.3% and the lifetime is increased by an average of 29.22%, compared to previous methods, while imposing little runtime overhead. Moreover, the proposed method prevents non-uniform (asymmetric) aging among FUs with the same type. The coefficient of variation of the aging rates of FUs with the same type is reduced by up to 91.36%.

A Power-Driven Stochastic-Deterministic Hierarchical High-Level Synthesis Framework for Module Selection, Scheduling and Binding

We present a power-driven hierarchical framework for module/functional-unit selection, scheduling, and binding in high level synthesis. A significant aspect of algorithm design for large and complex problems is arriving at tradeoffs between quality of solution and timing complexity. Towards this end, we integrate an improved version of the very runtime-efficient list scheduling algorithm called modified list scheduling (MLS) with a power-driven simulated annealing (SA) algorithm for module selection. Our hierarchical framework efficiently explores the problem solution space by an extensive exploration of the power-driven module-selection solution space via SA, and for each module selection solution, uses MLS to obtain a scheduling and (integrated) binding (S&B) solution in which the binding is either a regular one (minimizing number of FUs and thus FU leakage power) or power-driven with mux/demux power considerations. This framework avoids the very runtime intensive exploration of both module selection and S&B within a conventional SA algorithm, but retains the basic prowess of SA by exploring only the important aspect of power-driven module-selection in a stochastic manner. The proposed hierarchical framework provides an average of 9.5% FU leakage power improvement over state of the art (approximate) algorithms that optimize only FU leakage power, and has a smaller runtime by factors of 2.5–3x. Further, compared to a sophisticated flat simulated annealing framework and an optimal 0/1-ILP formulation for total (dynamic and leakage) FU and architecture power optimization under latency constraints, PSA-MLS provides an improvement of 5.3–5.8% with a runtime advantage of 2x, and has an average optimality gap of only 4.7–4.8% with a significant runtime advantage of a factor of more than 1900, respectively.

Reliability-Aware Resource Allocation and Binding in High-Level Synthesis

Soft error is nowadays a major reliability issue for nanoscale VLSI, and addressing it during high-level synthesis is essential to improve the efficiency of error mitigation. Motivated by the observation that for behavioral designs, especially control-flow intensive ones, variables and operations have non-uniform soft error vulnerabilities, we propose a novel reliability-aware allocation and binding technique to explore more effective soft error mitigation during high level synthesis. We first perform a comprehensive vulnerability analysis at the behavioral level by considering error propagation and masking in both control and data flows. Then the optimizations based on integer linear programming, as well as heuristic algorithm, are employed to incorporate the behavioral vulnerabilities into the register and functional unit binding phases to achieve cost-efficient error mitigation. The experimental results reveal that compared with the previous techniques which ignored behavioral vulnerabilities, the proposed approach can achieve up to 85% reliability improvement with the same amount of area budget in the RTL design.

Power-Aware High-Level Synthesis With Clock Skew Management

An effective clock-skew scheduling scheme in the high-level synthesis process targeted for power and speed optimization is presented. The proposed scheme has the following distinctive features: 1) a clock-skew management algorithm that selects a minimum set of clock phases to achieve the optimization goals is developed; 2) the effect of module binding in high-level synthesis was not considered in previous studies, which may lead to designs with timing violation; a discussion on how to model the effect of module binding is provided; 3) a heuristic low-power module binding algorithm that provides near-optimal results quickly is proposed; and 4) a technique called reallocation is proposed to exploit all available skews and thus maximize the capability of clock-skew scheduling. Experimental results show that, on the average, 48% power reduction is achieved by the proposed method. At most five clock phases are required, while in most cases two to four clock phases are sufficient.

Timing variation-aware scheduling and resource binding in high-level synthesis

Due to technological scaling, process variations have increased significantly, resulting in large variations in the delay of the functional units. Hence, the worst-case approach is becoming increasingly pessimistic in meeting a certain performance yield. The problem therefore is to increase the performance as much as possible while maintaining the desired yield. In this work, we introduce an integer linear programming (ILP) formulation for scheduling and resource binding in high-level synthesis (HLS) which tries to mitigate the effect of timing variations. In the presence of delay variations of resources, as chained resources can give a better latency and performance yield trade-off, instead of considering them independently, we consider external chaining of resources, that is, two or more resources are connected by external wiring, and exploit operation chaining. Without violating the yield constraints, the proposed ILP formulation chains two consecutive operations and binds these chained operations to chained resources for minimizing the overall latency of the schedule. Our ILP formulation also makes sure that two consecutive operations can be chained over multiple clock cycles so that it becomes possible to access the data in the middle of the chained operations at the start of the clock steps over which the operations are chained. By solving our ILP formulation using ILOG CPLEX, we show that our mechanism achieves lesser latency in most cases, compared to the no-chaining case. Significant performance improvement is achieved even for the 100% yield case, which has never been demonstrated in any published work, to the best of our knowledge.

THERMAL-AWARE HIGH-LEVEL SYNTHESIS BASED ON NETWORK FLOW METHOD

Controlling the chip temperature is becoming one of the important design considerations, since temperature adversely and seriously affects many of design qualities, such as reliability, performance and power of chip, and increases the packaging cost. In this work, we address a new problem of thermal-aware functional module binding in high-level synthesis, in which the objective is to minimize the peak temperature of the chip. Two key contributions are (1) to solve the binding problem with the primary objective of minimizing the "peak" switched capacitance of modules and the secondary objective of minimizing the "total" switched capacitance of modules and (2) to control the switched capacitances with respect to the floorplan of modules in a way to minimize the "peak" heat diffusion between modules. For (1), our proposed thermal-aware binding algorithm, called TA-b, formulates the thermal-aware binding problem into a problem of repeated utilization of network flow method, and solve it effectively. For (2), TA-b is extended, called TA-bf, to take into account a given floorplan information of functional modules, if exists, of modules to be practically effective. Through experiments using a set of benchmarks, it is shown that TA-bf is able to use 10.1°C and 11.8°C lower peak temperature on the average, compared to that of the conventional low-power and thermal-aware methods, which target to minimizing total switched capacitance only in Ref. 20 and to minimizing peak switched capacitance only in Ref. 16, respectively. Additionally, we confirm, from the experiments, that the reduced peak temperature saves leakage power significantly, implying that controlling chip temperature is critically important for reducing leakage current as well.

Module binding for low power clock gating

In synchronous sequential circuit design, clock gating is recognized as a useful technique to reduce the power consumption. Conventionally, the clock gating is synthesized after high-level synthesis. In this paper, we point out that the module binding in high-level synthesis has a significant impact on the power consumption of gated clock tree. Based on that observation, we use an integer linear program (ILP) to formally formulate the problem. Our objective is to find a module binding solution so that the power consumption (of gated clock tree) can be minimized. It is noteworthy to mention that our work is the first attempt to synthesize the clock gating in the high-level synthesis stage. Benchmark data consistently show that our approach can greatly improve the existing design flow.

Simultaneous scheduling, allocation and binding in high level synthesis

The authors describe a new and efficient algorithm for concurrent scheduling, allocation and binding in high level synthesis (HLS). Globally optimum data path realisations with efficient single-level interconnect structures are rapidly obtained using a novel strategy for the generation of new synthesis solutions applied to simulated annealing. An example of a fifth-order wave digital filter is included.

Incorporating performance and testability constraints during binding in high-level synthesis

Module and register binding during high-level synthesis is one of the most important steps in generating an RTL design from a behavioral description. The binding phase determines the structure of the final design, and hence issues related to area, performance and testability of the RTL design have to be addressed in this step. In this paper, we present algorithms for module and register binding which generate RTL designs having high performance and/or high testability. The binding problem is decomposed into a sequence of subproblems, each of which is modeled as a minimum-cost network flow problem. The relative impact of the possible bindings is expressed in terms of the costs associated with the edges of the network. The model is simple and can be solved quickly to obtain a low cost flow solution. Putting together the solutions to the subproblems gives low cost bindings. We also propose cost functions that can be used with varying emphasis on delay and testing. The results demonstrate the effectiveness of our algorithm; the final designs produced by the algorithms require a smaller clock cycle or are easier to test as compared to designs generated without the performance or testability constraints.