Binary-weighted DAC Research Articles

Minimum Unit Capacitance Calculation for Capacitor Arrays in Binary-Weighted and Split DACs

Minimum Unit Capacitance Calculation for Capacitor Arrays in Binary-Weighted and Split DACs

A 0.053 mm2 10-bit 10-ks/s 40-nW SAR ADC with pseudo single ended switching procedure for bio-related applications

This paper presents a power and area efficient pseudo single ended switching ADC for portable biomedical signal monitoring applications. The switching method features an 8-bit binary-weighted DAC array with a novel layout method called limited bottom-plate routing (LBPR) maintaining both feasibility and symmetry, a dynamic biased comparator and dynamic control logic. As a result, the proposed ADC saves 96.7% power consumption and 87.5% area occupation compared with conventional SAR ADC. Also, a novel DAC array layout method is promoted maintaining both feasibility and symmetry. A prototyped chip including a proposed ADC is fabricated in a 0.13 μm CMOS process. On condition of 0.6 V supply voltage and 10 kS/s sampling rate, the measured signal-to-noise-distortion (SNDR) and spurious free dynamic range (SFDR) are 57.8 dB and 64.3 dB, respectively. Besides, the ADC consumes only 40 nW power and 0.053 mm2 area achieving a figure-of-merit (FoM) of 6.26 fJ/conversion-step. Low power and low area occupation make it a good candidate for biomedical signal monitoring applications.

Dynamic Foreground Calibration of Binary-Weighted Current-Steering DAC

In this paper, a novel versatile calibration technique is proposed for current-steering binary-weighted DACs. This work is motivated by the fact that, in spite of the relative tendency to utilize the binary-weighted converters, there are very few calibration techniques dealing with their matching accuracy and transient performance. The introduced calibration technique can dynamically calibrate the DAC, in an arbitrary and repeated manner whenever needed. The system utilizes two clock pulses: the slow one for calibration and the other high-speed pulse for normal operation. The proposed calibration structure can strictly eliminate transistor mismatch-induced errors incorporating a unique calibration block utilized in an algorithmic manner for all current blocks. Implementing a configurable triple-path scheme, the current reference is updated by summing all of the adjusted LSB currents up, to calibrate the next upper MSB current. The transient behavior is improved due to the built-in intrinsic positive feedback-enabled deglitcher. Introducing tremendous overall current error as high as 125 LSB to the binary current blocks, the performance of the proposed calibration technique is validated for a 10-bit DAC by Cadence simulations utilizing TSMC 180-nm CMOS technology applying sampling frequency of 125 MHz for 1.8 V supply voltage and 500 nA LSB current.

Binary-Weighted DAC using W-2W Current Mirror Topology

Binary-Weighted DAC using W-2W Current Mirror Topology

Design and Implementation of a 46-kS/s CMOS SC Dual-Mode Capacitive Sensor Interface With 50-dB SNR and 0.7% Nonlinearity

This paper presents the design and implementation of a 46-kS/s CMOS switch-capacitor dual-mode capacitive sensor interface circuit for inkjet-printed capacitive humidity sensors. The specifications of the interface circuit, which includes a capacitance-to-voltage (C2V) converter combined with an analog-to-digital converter (ADC), are optimized at system level, emphasizing the C2V operation followed by the data converter. A closed form of the maximum output range of a single-stage C2V is provided to prevent cascade amplification. The gain-boosting technique is utilized in the operational transconductance amplifier design to improve the closed-loop linearity. The correlated double sampling technique attenuates the dc offset and low-frequency flicker noise from C2V. A 10-b successive approximation register ADC digitizes the output of C2V. The total area of the digital-to-analog (DAC) array is limited not only by the matching behavior, but also by the noise performance of C2V. The rail-to-rail ability is required to render the compatibility with various possible sensor inputs. A single-ended cascaded binary-weighted capacitive DAC is used to implement the charge redistribution binary search algorithm. The circuit is implemented in a 0.18- mu m CMOS technology and occupies an area of 1.2 mm(2). The tested prototype shows 0.69% nonlinearity in mode 1 and 1.38% nonlinearity in mode 2. The SNR of mode 1 is 50.1 dB and that of mode 2 is 36.5 dB, which meets the specification of 7.32 b in mode 1 and 5.32 b in mode 2. The total power consumption of the capacitive sensor interface is 70 mu W.

A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with on-chip reference voltage buffer

This paper presents the design of a 10-bit, 50MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an on-chip reference voltage buffer implemented in 65nm CMOS process. The speed limitation on SAR ADCs with off-chip reference voltage and the necessity of a fast-settling reference voltage buffer are elaborated. Design details of a high-speed reference voltage buffer which ensures precise settling of the DAC output voltage in the presence of bondwire inductances are provided. The ADC uses bootstrapped switches for input sampling, a double-tail high-speed dynamic comparator and split binary-weighted capacitive array charge redistribution DACs. The split binary-weighted array DAC topology helps us to achieve low area and less capacitive load and thus enhances power efficiency. Top-plate sampling is utilized in the DAC to reduce the number of switches. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25bits at a supply voltage of 1.2V, typical process corner and sampling frequency of 50MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697μW and achieves an energy efficiency of 25fJ/conversion-step while occupying a core area of 0.055mm2.

A compact 12-bit DAC with novel bias scheme

A compact and low-power design of a 12-bit binary-weighted current-steering DAC is presented. Instead of 4096 unit current cells, the proposed design uses 192 unit current sources with two reference currents. The silicon area of the generation circuit of two reference currents is very compact as well. The area of the total current source arrays is smaller than four times the area of 6-bit current source arrays, which has significantly reduced the dimension of the analog part of a conventional 12-bit DAC. The proposed DAC achieves 400MS/s update rate and consumes 38.7mW from single 1.8V supply.

Determining the reliable minimum unit capacitance for the DAC capacitor array of SAR ADCs

The layout area of an SAR ADC is mainly occupied by its DAC capacitor array. Since there are 2N matched unit capacitors employed for a binary-weighted N-bit DAC, selecting a small unit capacitance is the key to reducing the layout area of the capacitor array, and accordingly reduce the total area of an SAR ADC for size-constrained implantable or wearable applications. In this paper the matching error and thermal noise of the capacitor array are considered systematically for the whole SAR ADC to determine the minimum unit capacitance. The statistical analysis shows that the matching error of the capacitor array depends not only on the matching parameter of the given process but also on the confidence level of the design, while thermal noise analysis shows that thermal noise of the capacitor array does not equal that of either the unit capacitor or the total capacitance of the capacitor array. The calculations for the matching error and thermal noise of a 10-bit DAC show that although the matching error is 7 times bigger, thermal noise which consumes 1/8 error budget should not be ignored for determining the reliable minimum unit capacitance. An iterative algorithm is proposed to find the minimum value when both matching error and thermal noise are considered. A 10-bit SAR ADC adopting an 89.44fF poly–poly unit capacitor in the 0.35μm CMOS process validated the method.

A 3.5 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modulation Profile

A frequency-locked loop (FLL) based spread-spectrum clock generator (SSCG) with a memoryless Newton-Raphson modulation profile is introduced in this paper. The SSCG uses an FLL as a main clock generator. It brings not only an area reduction to the SSCG but also the advantage of having multiple frequency deviations. A double binary-weighted DAC is proposed that modulates the frequency information of the frequency detector using a 1-1-1 MASH <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\Delta \Sigma$</tex></formula> modulator. The Newton-Raphson mathematical algorithm is applied to the proposed profile generator in order to generate the optimized nonlinear profile without needing any memory, resulting in a reduction in the area and the power consumption. It also makes it possible to have multiple modulation frequencies. The SSCG can support 14 frequency deviations of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\pm 0.5\%$</tex></formula> to 3.5% in steps of 0.5% and three modulation frequencies of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$f _{\rm m}$</tex></formula> , <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$2 f _{\rm m}$</tex></formula> and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$3 f _{\rm m}$</tex></formula> . It achieved an EMI reduction of 19.14 dB with a 0.5% down spreading and a 31 kHz modulation frequency, while employing a core area of 0.076 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\hbox{mm}}^{2}$</tex> </formula> in a 0.13- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu{\hbox{m}}$</tex> </formula> CMOS process and consuming 23.72 mW at 3.5 GHz.

A Compact Dynamic-Performance-Improved Current-Steering DAC With Random Rotation-Based Binary-Weighted Selection

Conventional binary-weighted current-steering DACs are generally operated with current groups where each group is binary-weighted and formed with predetermined members of a unit current-source array. This paper proposes a random rotation-based binary-weighted selection (RRBS) that efficiently performs dynamic-element matching (DEM) by randomly rotating the sequence of these units to form new binary-weighted current groups for each DAC output. Without using binary-to-thermometer decoders, RRBS features its simplicity and compactness of DEM realization. Compared to conventional binary-weighted DACs, RRBS DACs are insensitive to the mismatch of small-size current-sources and exhibit better dynamic performance. A 10-bit RRBS DAC is implemented with only 0.034 mm2 in a standard 1P6M 1.8 V 0.18 μm CMOS process. Measured performance achieves >;61 dB spurious-free dynamic range (SFDR) in the Nyquist bandwidth with 500 MS/s, while its active area is less than one-tenth of that required by state-of-the-art 10-bit current steering DACs. To the best of our knowledge, the proposed RRBS implements the smallest area for high-speed current-steering DACs up to now. Its SFDR is also comparable to that of 12-bit published designs. Three popular figures-of-merit (FOMs) are used to compare this design with other state-of-the-art 10-12-bit DACs, with the proposed design performing best with 2 FOMs.