Binary Signed-digit Representation Research Articles

Non-Standard Binary Representations and the Stern Sequence

We show that the number of short binary signed-digit representations of an integer $n$ is equal to the $n$-th term in the Stern sequence. Various proofs are provided, including direct, bijective, and generating function proofs. We also show that this result can be derived from recent work of Monroe on binary signed-digit representations of a fixed length.

Limits of real numbers in the binary signed digit representation

We extract verified algorithms for exact real number computation from constructive proofs. To this end we use a coinductive representation of reals as streams of binary signed digits. The main objective of this paper is the formalisation of a constructive proof that real numbers are closed with respect to limits. All the proofs of the main theorem and the first application are implemented in the Minlog proof system and the extracted terms are further translated into Haskell. We compare two approaches. The first approach is a direct proof. In the second approach we make use of the representation of reals by a Cauchy-sequence of rationals. Utilizing translations between the two represenation and using the completeness of the Cauchy-reals, the proof is very short. In both cases we use Minlog's program extraction mechanism to automatically extract a formally verified program that transforms a converging sequence of reals, i.e.~a sequence of streams of binary signed digits together with a modulus of convergence, into the binary signed digit representation of its limit. The correctness of the extracted terms follows directly from the soundness theorem of program extraction. As a first application we use the extracted algorithms together with Heron's method to construct an algorithm that computes square roots with respect to the binary signed digit representation. In a second application we use the convergence theorem to show that the signed digit representation of real numbers is closed under multiplication.

BINARY SIGNED-DIGIT REPRESENTATIONS IN PAPERFOLDING

AbstractWhen a page, represented by the interval $[0,1]$ , is folded right over left $n $ times, the right-hand fold contains a sequence of points. We specify these points using two different representation techniques, both involving binary signed-digit representations.

Binary signed-digit integers and the Stern diatomic sequence

Stern's diatomic sequence is a well-studied and simply defined sequence with many fascinating characteristics. The binary signed-digit representation of integers is an alternative representation of integers with much use in efficient computation, coding theory and cryptography. We link these two ideas here, showing that the number of $i$-bit binary signed-digit representations of an integer $n$ with $n<2^i$ is the $(2^i-n)^\text{th}$ element in Stern's diatomic sequence. This correspondence makes the vast range of results known for Stern's diatomic sequence available for consideration in the study of binary signed-digit integers.

Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation

Fast Fourier transform (FFT) coprocessor, having a significant impact on the performance of communication systems, has been a hot topic of research for many years. The FFT function consists of consecutive multiply add operations over complex numbers, dubbed as butterfly units. Applying floating-point (FP) arithmetic to FFT architectures, specifically butterfly units, has become more popular recently. It offloads compute-intensive tasks from general-purpose processors by dismissing FP concerns (e.g., scaling and overflow/underflow). However, the major downside of FP butterfly is its slowness in comparison with its fixed-point counterpart. This reveals the incentive to develop a high-speed FP butterfly architecture to mitigate FP slowness. This brief proposes a fast FP butterfly unit using a devised FP fused-dot-product-add (FDPA) unit, to compute AB ± CD ± E, based on binary-signed-digit (BSD) representation. The FP three-operand BSD adder and the FP BSD constant multiplier are the constituents of the proposed FDPA unit. A carry-limited BSD adder is proposed and used in the three-operand adder and the parallel BSD multiplier so as to improve the speed of the FDPA unit. Moreover, modified Booth encoding is used to accelerate the BSD multiplier. The synthesis results show that the proposed FP butterfly architecture is much faster than previous counterparts but at the cost of more area.

On the number of binary signed digit representations of a given weight

Binary signed digit representations (BSDR's) of integers have been studied since the 1950's. Their study was originally motivated by multiplication and division algorithms for integers and later by arithmetics on elliptic curves. Our paper is motivated by differential cryptanalysis of hash functions. We give an upper bound for the number of BSDR's of a given weight. Our result improves the upper bound on the number of BSDR's with minimal weight stated by Grabner and Heuberger in On the number of optimal base $2$ representations, Des. Codes Cryptogr. 40 (2006), 25--39, and introduce a new recursive upper bound for the number of BSDR's of any given weight.

Radix-2 Division Algorithms with an Over-Redundant Digit Set

This paper presents a derivation of four radix-2 division algorithms by digit recurrence. Each division algorithm selects a quotient digit from the over-redundant digit set {−2, −1, 0, 1, 2}, and the selection of each quotient digit depends only on the two most-significant digits of the partial remainder in a redundant representation. Two algorithms use a two’s complement representation for the partial remainder and carry-save additions, and the other two algorithms use a binary signed-digit representation for the partial remainder and carry-free additions. Three algorithms are novel. The fourth algorithm has been presented before. Results from the synthesized netlists show that two of our fastest algorithms achieve an improvement of 10 percent in latency per iteration over a standard radix-2 SRT algorithm at the cost of 36 percent more power and 50 percent more area.

A Common Subexpression Elimination Tree Algorithm

A common subexpression elimination algorithm is proposed to minimize the complexity of the multiple constant multiplication operation. The coefficients (constants) of the multiple constant multiplication are represented using the binary signed digit number system. The binary signed digit representations of each coefficient are enumerated using the representation tree. The algorithm traverses the tree to calculate the possible subexpressions at each node. Each subexpression is used to find a possible decomposition for the coefficient to be encoded. A complexity formula is proposed to compare the decompositions. The algorithm is designed to prune the tree when it finds a decomposition with minimum complexity. This reduces the search space while minimizing the hardware complexity. Results show that the algorithm has better performance than other published algorithms including linear programming optimization methods. The algorithm outperforms the subexpression sharing method in that uses only the canonical signed-digit representations.

Fast calculation of number of binary signed digit representations of an integer

Binary Signed Digit(BSD) representation of an integer is widely used in computer arithmetic,cryptography and digital signal processing.An integer of length n bits can have several BSD representations.In this paper,the authors studied the properties of the number of BSD representation of an integer,and presented two improved non-recursion algorithms.They can rapidly calculate the exact number of BSD representations of an integer of a certain length,and the storage requirements get reduced.

Efficient realisation of arithmetic algorithms with weighted collection of posibits and negabits

Most common uses of negatively weighted bits (negabits), normally assuming arithmetic value 21(0) for logical 1(0) state, are as the most significant bit of 2's-complement numbers and negative component in binary signed-digit (BSD) representation. More recently, weighted bit-set (WBS) encoding of generalised digit sets and practice of inverted encoding of negabits (IEN) have allowed for easy handling of any equally weighted mix of negabits and ordinary bits (posibits) via standard arithmetic cells (e.g., half/full adders, compressors, and counters), which are highly optimised for a host of simple and composite figures of merit involving delay, power, and area, and are continually improving due to their wide applicability. In this paper, we aim to promote WBS and IEN as new design concepts for designers of computer arithmetic circuits. We provide a few relevant examples from previously designed logical circuits and redesigns of established circuits such as 2's-complement multipliers and modified booth recoders. Furthermore, we present a modulo-(2 n + 1) multiplier, where partial products are represented in WBS with IEN. We show that by using standard reduction cells, partial products can be reduced to two. The result is then converted, in constant time, to BSD representation and, via simple addition, to final sum.

Proofs, Programs, Processes

The objective of this paper is to provide a theoretical foundation for program extraction from inductive and coinductive proofs geared to practical applications. The novelties consist in the addition of inductive and coinductive definitions to a realizability interpretation for first-order proofs, a soundness proof for this system, and applications to the synthesis of non-trivial provably correct programs in the area of exact real number computation. We show that realizers, although per se untyped, can be assigned polymorphic recursive types and hence represent valid programs in a lazy functional programming language such as Haskell. Programs extracted from proofs using coinduction can be understood as perpetual processes producing infinite streams of data. Typical applications of such processes are computations in exact real arithmetic. As an example we show how to extract a program computing the average of two real numbers w.r.t. the binary signed digit representation.

From coinductive proofs to exact real arithmetic: theory and applications

Based on a new coinductive characterization of continuous functions we extract certified programs for exact real number computation from constructive proofs. The extracted programs construct and combine exact real number algorithms with respect to the binary signed digit representation of real numbers. The data type corresponding to the coinductive definition of continuous functions consists of finitely branching non-wellfounded trees describing when the algorithm writes and reads digits. We discuss several examples including the extraction of programs for polynomials up to degree two and the definite integral of continuous maps.

On optimal binary signed digit representations of integers

Binary signed digit representation (BSD-R) of an integer is widely used in computer arithmetic, cryptography and digital signal processing. This paper studies what the exact number of optimal BSD-R of an integer is and how to generate them entirely. We also show which kinds of integers have the maximum number of optimal BSD-Rs.

Differential Power Analysis on Countermeasures Using Binary Signed Digit Representations

Side channel attacks are a very serious menace to embedded devices with cryptographic applications. To counteract such attacks many randomization techniques have been proposed. One efficient technique in elliptic curve cryptosystems randomizes addition chains with binary signed digit (BSD) representations of the secret key. However, when such countermeasures have been used alone, most of them have been broken by various simple power analysis attacks. In this paper, we consider combinations which can enhance the security of countermeasures using BSD representations by adding additional countermeasures. First, we propose several ways the improved countermeasures based on BSD representations can be attacked. In an actual statistical power analysis attack, the number of samples plays an important role. Therefore, we estimate the number of samples needed in the proposed attack.

Computational efficiency analysis of Wu et al.’s fast modular multi-exponentiation algorithm

Very recently, for speeding up the computation of modular multi-exponentiation, Wu et al. presented a fast algorithm combining the complement recoding method and the minimal weight binary signed-digit representation technique. They claimed that the proposed algorithm reduced the number of modular multiplications from 1.503 k to 1.306 k on average, where the value k is the maximum bit-length of two exponents. However, in this paper, we show that their claim is unwarranted. We analyze the computational efficiency of Wu et al.’s algorithm by modeling it as a Markov chain. Our main result is that Wu et al.’s algorithm requires 1.471 k modular multiplications on average.

On binary signed digit representations of integers

Applications of signed digit representations of an integer include computer arithmetic, cryptography, and digital signal processing. An integer of length n bits can have several binary signed digit (BSD) representations and their number depends on its value and varies with its length. In this paper, we present an algorithm that calculates the exact number of BSDR of an integer of a certain length. We formulate the integer that has the maximum number of BSDR among all integers of the same length. We also present an algorithm to generate a random BSD representation for an integer starting from the most significant end and its modified version which generates all possible BSDR. We show how the number of BSD representations of k increases as we prepend 0s to its binary representation.

Fast modular multi-exponentiation using modified complex arithmetic

Modular multi-exponentiation ∏ i = 1 n M i E i ( mod N ) is a very important but time-consuming operation in many modern cryptosystems. In this paper, a fast modular multi-exponentiation is proposed utilizing the binary-like complex arithmetic method, complement representation method and canonical-signed-digit recoding technique. By performing complements and canonical-signed-digit recoding technique, the Hamming weight (number of 1’s in the binary representation or number of non-zero digits in the binary signed-digit representations) of the exponents can be reduced. Based on these techniques, an algorithm with efficient modular multi-exponentiation is proposed. For modular multi-exponentiation, in average case, the proposed algorithm can reduce the number of modular multiplications (MMs) from 1.503 k to 1.306 k, where k is the bit-length of the exponent. We can therefore efficiently speed up the overall performance of the modular multi-exponentiation for cryptographic applications.

Enhanced Exhaustive Search Attack on Randomized BSD Type Countermeasure

We propose a new analysis technique against a class of countermeasure using randomized binary signed digit (BSD) representations. We also introduce some invariant properties between BSD representations. The proposed analysis technique can directly recover the secret key from power measurements without information for algorithm because of the invariant properties of BSD representation. Thus the proposed attack is applicable to all countermeasures using BSD representations. Finally, we give the simulation results against some countermeasures using BSD representation such as Ha-Moon method, Ebeid-Hasan method, and the method of Agagliate et al. The results show that the proposed attack is practical analysis method.

Low-error carry-free fixed-width multipliers with low-cost compensation circuits

In this paper, we propose a low-error fixed-width redundant multiplier design. The design is based on the statistical analysis of the error compensation value of the truncated partial products in binary signed-digit representation with modified Booth encoding. The overall truncation error is significantly reduced compared with other previous approaches. Furthermore, the derived relationship between the compensation value and the truncated digits is so simple that the area cost of the corresponding compensation circuit is almost negligible. The fixed-width multiplier design is also applied to the discrete cosine transform/inverse discrete cosine transform (DCT/IDCT) computation in JPEG image compression.

Algorithm of asynchronous binary signed-digit recoding on fast multiexponentiation

Multiexponentiation, for the 2-dimension one especially, is a very important but time-consuming operation in many ElGamal-like public key cryptosystems. An efficient multiexponentiation method is firstly proposed by Shamir in ElGamal’s paper. Shamir’s method requires 1.75 n modular multiplications in average, where n is the bit-length of the exponents. Using minimal weight binary signed-digit (BSD) representations in Shamir’s method can reduce the number of multiplications to 1.556 n. Due to there are many minimal weight BSD representations for an integer, Dimitrov et al. proposed a new 2-dimension multiexponentiation algorithm to recode the canonical binary signed-digit representations. The average number of the number 1.556 n is reduced to 1.534 n. After the publish of the Dimitrov–Jullien–Miller algorithm, there are many research on receding BSD representation of a pair of integers. The most interesting one is the joint sparse form. The number of multiplication can be reduced to 1.500 n in joint sparse form when the exponent length is near infinite. In this paper, we propose a new asynchronous recoding algorithm to reduce the factor to 1.509n. For comparison to all the previous algorithm, the property of asynchronous receding is especially suitable for multi-dimension multiexponentiation.