Binary Signed-digit Adder Research Articles

Efficient error detection and correction method for 1-out-of-3 binary signed digit adders

ABSTRACTBinary Signed Digit (BSD) number system has been extensively used in high-speed applications due to taking carry-free adders and high-speed multipliers. The 1-out-of-3 BSD encoding is an inherently fault-tolerant BSD encoding, which is a subset of m-out-of-n codes widely employed for error detection and correction. Although some fault-tolerant methods have been already proposed for 1-out-of-3 BSD adder, an efficient structure with both capabilities of fault detection and correction has not been introduced yet. In this paper, a 1-out-of-3 BSD adder with error detection and correction capabilities is presented. In spite of the negligible penalties in delay, power consumption, and area overhead, synthesis results show that more fault tolerance capability is achieved by the proposed method.

Design, Evaluation and Application of Approximate High-Radix Dividers

Approximate high radix dividers (HR-AXDs) are proposed and investigated in this paper. High-radix division is reviewed and inexact computing is introduced at different levels. Design parameters such as number of bits (N) and radix (r) are considered in the analysis; the replacement of exact cells with inexact cells in a binary signed-digit adder is introduced by utilizing different replacement schemes. Cell truncation and error compensation are also proposed to further extend inexact computation. Circuit-level performance and the error characteristics of the inexact high radix dividers are analyzed for the proposed designs. The combined assessment of the normal error distance, power dissipation, and delay is investigated and applications of approximate high-radix dividers are treated in detail. The simulation results show that the proposed approximate dividers offer extensive saving in terms of power dissipation, circuit complexity, and delay, while only incurring in a small degradation in accuracy thus making them possibly suitable and interesting to some applications and domains such as low power/mobile computing.

EFFICIENT FLOATING POINT FAST FOURIER TRANSFORM BUTTERFLY ARCHITECTURE USING BINARY SIGNED DIGIT MULTIPLIER AND ADDERS

Fast Fourier transform (FFT) is one of the most important tools in digital signal processing as well as communication system because transforming time domain to S-plane is very convenient using FFT. As FFT uses various techniques to convert a signal from time domain to S-domain and inverse, out of which butterfly technique is the one on which paper is focused on. Butterfly technique uses additions and multiplications of operands to get the required output. Floating point (FP) is used as operands due to their flexibility. As the computations involving FP has less speed, we have used binary signed digit (BSD). BSD will take the less time for addition and subtraction. Three bit BSD adder and FP adder together will make a fused dot product add (FDPA) unit. In FDPA, unit addition and subtraction will be one group and multiplication will be one group and then their respective results will be fused. Modified booth encoding and decoding algorithm are used here to make the complex multiplication with ease.

Efficient Low-Cost Fault-Localization and Self-Repairing Radix-2 Signed-Digit Adders Applying the Self-Dual Concept

Signed-digit adder, which eliminates carry propagation chain, can execute addition operation independent of the length of operands, in constant time. The confined carry propagation implies remarkable advantage in terms of error detection, localization, and correction. We developed a new low-cost technique, for fault-localization and error-correction, which utilizes the self-dual concept in binary signed-digit adders. The foundational idea of our technique is that the designed method, when fed by the complement of its functional input under the existence of a stuck-at fault, yields a fault-free inverse of the expected output. In this method, after detection of a fault, the method continues with input inversion, recomputation, and desired output inversion. The faulty component will localize by comparison of the faulty and fault-free outputs. Higher reliability with less computational time and reduced hardware-area overhead are the distinct features of this new design. In this method, all of the single stuck-at faults can be localized and corrected, whereas previous approaches were unable to localize and correct with 100 % reliability even with longer time durations and greater hardware cost. The experimental results prove that our design requires 20 %–90 % less time and 20 %–40 % smaller area overhead compared with a previous related work.

Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation

Fast Fourier transform (FFT) coprocessor, having a significant impact on the performance of communication systems, has been a hot topic of research for many years. The FFT function consists of consecutive multiply add operations over complex numbers, dubbed as butterfly units. Applying floating-point (FP) arithmetic to FFT architectures, specifically butterfly units, has become more popular recently. It offloads compute-intensive tasks from general-purpose processors by dismissing FP concerns (e.g., scaling and overflow/underflow). However, the major downside of FP butterfly is its slowness in comparison with its fixed-point counterpart. This reveals the incentive to develop a high-speed FP butterfly architecture to mitigate FP slowness. This brief proposes a fast FP butterfly unit using a devised FP fused-dot-product-add (FDPA) unit, to compute AB ± CD ± E, based on binary-signed-digit (BSD) representation. The FP three-operand BSD adder and the FP BSD constant multiplier are the constituents of the proposed FDPA unit. A carry-limited BSD adder is proposed and used in the three-operand adder and the parallel BSD multiplier so as to improve the speed of the FDPA unit. Moreover, modified Booth encoding is used to accelerate the BSD multiplier. The synthesis results show that the proposed FP butterfly architecture is much faster than previous counterparts but at the cost of more area.

HIGH-SPEED MODULAR MULTIPLIERS BASED ON A NEW BINARY SIGNED-DIGIT ADDER TREE STRUCTURE

Modular multiplication is a very important arithmetic operation in residue-based real-time computing systems. In this paper, we present multipliers using a modified binary tree of the modulo m signed-digit (SD) number adders where m = 2n + μ(μ = ±1, 0). To simplify the residue SD adder, new addition rules are used for generating the intermediate sum and carry with an 1-bit binary encoded number representation. By using the new encoding method, the proposed residue addition requires less hardware and shorter delay time than previous one. A modulo m multiplier can be implemented by a binary modulo m adder tree which has a depth of log 2 n. In order to introduce a binary SD adder tree with the new addition rules, two novel modulo m adders have been proposed in this paper. Finally, the evaluation apparently shows that the proposed two kinds of modulo m adders are performed more efficiency by comparing with the modulo SD adder which is mentioned in our previous work, and a new binary SD adder tree structure has been proposed.

SRT Division Based on Redundant Signed Number

SRT division schemes are presented based on a redundant number operand format aiming high speed operation. The proposed SRT division method based on a redundant binary adder (RBA) and one based on a recoded binary signed digit adder (RBSDA) show a 33% and 50% speed improvement, respectively. The time complexity of the proposed division based on redundant number is O(n); importantly, the redundant number based design is easy to implement due to its structural regularity.