Binary Search Analog To Digital Converter Research Articles

A 13.8pJ/conv-step binary search ADC with reusable comparator architecture

This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step.

A reusable stage based reduced comparator count binary search ADC

A 4- bit reusable stage based asynchronous binary search analog to digital converter (ADC) with a smart switching network, and reduced comparator count is presented in this paper. The proposed ADC uses asynchronous logic to activate comparators sequentially while switching network is used to provide reference voltages for selected comparators. In the extended version, the 6-bit ADC is designed using only $$(\mathrm{N}+1)$$ comparators instead of $$2^{(N)}-1$$ and (2N − 1) as used in conventional approach. The simulation results of 4 bit ADC confirms that the design achieves conversion speed of 500 MSPS with power consumption of 1.63 mW when operated on 1.8 V supply with SNR, SFDR and ENOB as 22.5 dB, 32.4 dBc and 3.8 bits while for 6 bit the SNR, SFDR and ENOB are 34.96 dB, 42 dBc and 5.56 bits respectively with 0.35 mW of power dissipation. The Walden FOM for proposed 4 bit and 6 bit ADC design are 0.21 pJ/conversion-step and 24.7 fJ/conversion-step respectively.

An Asynchronous Binary-Search ADC Architecture With a Reduced Comparator Count

This paper reports an asynchronous binary-search analog-to-digital converter (ADC) with reference range prediction. An original N-bit binary-search ADC requires 2N - 1 comparators while the proposed one only needs 2N - 1 ones. Compared to the (high speed, high power) flash ADC and (low speed, low power) successive approximation register ADC, the proposed architecture achieves the balance between power consumption and operation speed. The proof-of-concept 5-bit prototype only consists of a passive track-and-hold circuit, a reference ladder, 9 comparators, 56 switches and 26 static logic gates. This compact ADC occupies an active area of 120 × 50 μm2 and consumes 1.97 mW from a 1-V supply. At 800 MS/s, the effective number of bits is 4.40 bit and the effective resolution bandwidth is 700 MHz. The resultant figure of merit is 116 fJ/conversion-step.