Size Of Binary Decision Diagrams Research Articles

Diversity enforced Genetic Algorithm (GA) for Binary Decision Diagram (BDD) reordering

Binary Decision Diagrams (BDDs) have become the state-of-art data structures in numerous fields, wherein, small-sized BDDs are required to reduce the companion cost. Since BDD size is sensitive to the order of variables for the Boolean function in use, evolutionary algorithms have been extensively exploited to solve the BDD reordering problem which is provably an NP-hard problem. However, getting trapped in a local minima is more likely as the population gets homogeneous during the evolution of the algorithm. This paper compares various diversity measures correlated to BDDs and studies the impact of different crossover and mutations used in the Genetic Algorithm (GA) on those diversity measures. Thereafter, we propose an enhanced GA-based reordering algorithm for BDD, wherein, the chosen diversity measure is calculated per generation to steer the application of proper variation operators, in such a way that an acceptable level of equilibrium between exploration and exploitation is preserved. Finally, we utilize a new heuristic Cyclic Crossover (HCX) that further improves the performance of the proposed algorithm following the fitness value. Experimental results on public benchmarks show that our proposed algorithm outperforms other algorithms from the literature when switching between HCX and swap mutation operators is made following the measured diversity metric.

A Genetic Algorithm (GA) and Swarm-Based Binary Decision Diagram (BDD) Reordering Optimizer Reinforced With Recent Operators

The use of Binary Decision Diagrams (BDDs) has proliferated in numerous fields. When a system criterion is formulated in form of a Boolean function, its BDD is constructed. Each node in the BDD is further mapped into another form to be exploited in the system analysis. However, the cost of the resultant mapping form is directly related to the BDD size which can be effectively reduced through applying proper variable reordering followed by applying reduction rules that preserve the fidelity of the BDD in correctly representing the input Boolean function. Although several algorithms have been proposed in the literature to find the optimal order of variables in the BDD, the scalability of such algorithms is a serious barrier when it comes to complex systems with exponential explosion in the possible number of orders in the search space. Furthermore, solely exploring the search space in BDD reordering is not sufficient since better permutations might be obtained with slight tuning of the candidate solutions. Thus, a sufficient degree of equilibrium between exploration and exploitation should be preserved during the evolution of the reordering algorithm. In this paper, we propose a BDD optimizer driven by either Genetic Algorithm (GA) or swarm engines. The proposed GA-based BDD reordering optimizer iteratively processes an essentially large population with a randomized mixing of low destructive crossover/mutation operators. The proposed swarm-based optimizer, on the other hand, maps a vector of real numbers into a permutation to further construct its companion BDD. The generation of the next vector is guided by recent parameter and parameter-less swarm algorithms that are armed with effective mechanisms to simultaneously conduct exploration and exploitation. Experimental results show that our proposed optimizer effectively reduces the resultant BDD size for input Boolean functions with almost linear computational complexity. Furthermore, it has been found that exploiting recent swarm optimizers with spiral movement in BDD reordering problem can outperform GA for large scale Boolean functions. Finally, as a real-world application, our proposed algorithm is applied to reversible logic synthesis to show the achieved reduction in the Quantum Cost (QC) associated with BDD-based synthesis.

Formal Verification of Integer Multiplier Circuits Using Binary Decision Diagrams

Multiplier circuit covers a more extensive area of embedded system application in digital signal processing, cryptography, and multimedia. Nonstandard implementations and custom optimization are being done to reduce the size of multipliers. The circuit became prone to a buggy, and hence the demand for verification increased. Formal verification methods, such as satisfiability (SAT), symbolic computer algebra (SCA), and binary decision diagrams (BDDs) have made massive progress over the last few decades. However, these methods are insufficient to verify the optimized multipliers. SAT-based equivalence checking is computationally expensive. SCA-based backward rewriting is limited to algebraic-friendly multipliers. The complexity of BDDs is exponential with the input size. Although, by allowing an additional variable method, the size of the BDD is limited to 4th degree polynomial of the number of the inputs, this method is not explored to verify optimized multipliers. This article focus on verifying integer multipliers with diverse architectures. We propose an algorithm for the direct construction of BDDs without traversing circuits and generate BDDs up to 1024 bits. We utilize the additional variable method and constructing BDDs using high-to-low variable ordering. We reduce the complexity of BDD size to a 3rd degree polynomial. We generate BDDs and verify the multipliers with various architectures up to 64 bits. We propose a method to verify optimized multipliers by checking equivalence and verifying up to 32-bits optimized multipliers. We do the error tolerance analysis of our approach by inserting bugs in a circuit at various locations.

BDD-Based Error Metric Analysis, Computation and Optimization

Approximate Computing is a design paradigm that trades off computational accuracy for gains in non-functional aspects such as reduced area, increased computation speed, or power reduction. Computing the error of the approximated design is an essential step to determine its quality. The computation time for determining the error can become very large, effectively rendering the entire logic approximation procedure infeasible. In this work we extensively analyze various error metrics and approximation operations. We present methods to accelerate the computation of error metric computations by 1) exploiting structural information of the function obtained by applying the analyzed operations and 2) computing estimates of the metrics for multi-output Boolean functions represented as Binary Decision Diagrams (BDDs). We further present a novel greedy, bucket-based BDD minimization framework employing the newly proposed error metric computations to produce Pareto-optimal solutions with respect to BDD size and multiple error metrics. The applicability of the proposed minimization framework is demonstrated by an experimental evaluation. We can report considerable speedups while, at the same time, creating high-quality approximated BDDs. The presented framework is publicly available as open-source software on GitHub.

A fast Binary Decision Diagram (BDD)-based reversible logic optimization engine driven by recent meta-heuristic reordering algorithms

Reversible logic has recently gained a remarkable interest due to its information lossless property, which minimizes power dissipation in the circuit. Furthermore, with their natural reversibility, quantum computations can profit from the advances in reversible logic synthesis, as the latter can be easily applied to map practical logic designs to quantum architectures. Although numerous algorithms have been proposed to synthesize reversible circuits with low cost, the increasing demands for scalable synthesis techniques represent a serious barrier in the synthesis process. Furthermore, the enhanced reliability of the synthesized circuits comes at the cost of redundancy in the quantum architecture of the gates composing that circuit, which increases the overall manufacturing cost for fault-tolerant circuits. Binary Decision Diagram (BDD) based synthesis has demonstrated a great evidence in reversible logic synthesis, due to its scalability in synthesizing complex circuits within a reasonable time. However, the cost of the synthesized circuit is roughly correlated to its corresponding BDD size. In this paper, we propose a fast reversible circuit synthesis methodology driven by a BDD-reordering optimization engine implemented by recent meta-heuristic optimization algorithms. Experimental results show that Genetic Algorithm (GA) based reordering supported with Alternating Crossover (AX) and swap mutation outperforms others as it is the least destructive for low-cost BDDs during the optimization recipe.

Exact Modeling of Binary Decision Diagram Complexity

An exact model of Binary Decision Diagram (BDD) complexity is derived in this paper. An estimate of BDD complexity using models has already been proposed. The estimated BDD complexity in previous papers is just an approximation of experimental data using a curve that fits the data. Mathematical analysis indicates that many curves can be fitted to the same data. This paper derives the exact model for the BDD complexity by analysis. In order to derive the exact model, relation between the SOP (Sum Of Product) terms and Min-terms was analyzed. Further the variation of BDD size for various Min-terms was also analyzed. Finally the plot between the experimental BDD size and the derived exact model proves the accuracy of the derived model.

A New Empirical Evaluation of Existing Methods for Estimating BDD Sizes

Binary Decision Diagrams (BDDs) are very useful structures to represent Boolean function in VLSI synthesis. Time taken to build a BDD and obtaining its size plays a major role in the time of complexity of VLSI synthesis. This time complexity increases drastically as the number of input variables increases. Various models to estimate the size of the BDD, without actually building it already exists. These models claim to support both simplified and un-simplified Boolean functions. The models were developed under the justification that time to estimate will be far less compared to the time taken to actually build the BDD. There are two drawbacks with the existing model. First drawback is that, the current model just follows a random curve fit without any substantial mathematical support. Second drawback is the existing model is based on experimental results which used only less than ten variables. Since current practical functions may use hundreds of variables, there is no guarantee that the model is accurate enough. Given the two drawbacks, it becomes necessary to test the existing model for more complex circuits with hundreds of variables. In this paper the existing models were tested with standard benchmark circuits. Results were compared with actual BDD sizes of the benchmarks and the estimated sizes from the parameters of the benchmarks. Comparison of the results proved that existing models give poor results for the circuits with more than ten variables and existing models become inapplicable to most of the current practical functions that uses more than hundreds of variables.

Using reliability analysis to support decision making in phased mission systems

AbstractBecause of the environments in which they will operate, future autonomous systems must be capable of reconfiguring quickly and safely following faults or environmental changes. Past research has shown how, by considering autonomous systems to perform phased missions, reliability analysis can support decision making by allowing comparison of the probability of success of different missions following reconfiguration. Binary decision diagrams (BDDs) offer fast, accurate reliability analysis that could contribute to real‐time decision making. However, phased mission analysis using existing BDD models is too slow to contribute to the instant decisions needed in time‐critical situations. This paper investigates 2 aspects of BDD models that affect analysis speed: variable ordering and quantification efficiency. Variable ordering affects BDD size, which directly affects analysis speed. Here, a new ordering scheme is proposed for use in the context of a decision‐making process. Variables are ordered before a mission, and reordering is unnecessary no matter how the mission configuration changes. Three BDD models are proposed to address the efficiency and accuracy of existing models. The advantages of the developed ordering scheme and BDD models are demonstrated in the context of their application within a reliability analysis methodology used to support decision making in an unmanned aerial vehicle.

Symbolic Supervisory Control of Timed Discrete Event Systems

We symbolically compute a nonblocking, controllable, and minimally restrictive supervisor for timed discrete event systems (TDESs), in the supervisory control theory context. We model TDES based on timed extended finite automata (TEFAs): an augmentation of extended finite automata (EFAs) by incorporating discrete time into the model. EFAs are ordinary automata extended with discrete variables, where conditional expressions and update functions can be attached to the transitions. The controllability is defined based on the corresponding tick models of the TEFAs. A tick can be considered as an event that is generated by a global digital clock. The tick models suffer from a major problem: the state size is very sensitive to the clock frequency. We show how a controllable supervisor, equivalent to the one computed based on the tick models, can be obtained by eliminating the tick events. To tackle large problems, all computations are conducted symbolically using binary decision diagrams (BDDs). We show that, based on the proposed approach, a fixed point is reached earlier in the reachability analysis and that the size of the intermediate BDDs usually becomes smaller. The framework has been applied to a real industrial application and several benchmarks.

A New Method for Modeling on Concurrent System

Binary decision diagrams (BDDs) are effective means to cope with complex concurrent system. But the size of BDD itself can be relatively large. We study the BDD representation of large synchronous, asynchronous and interleaved processes with communication via shared variables. Due to the features of communication, we introduce a novel represen- tation strategy. Based on the model, we continue to model and map up the synchrony, and detect the deadlock errors.

BDD Ordering Heuristics for Classical Planning

Symbolic search using binary decision diagrams (BDDs) can often save large amounts of memory due to its concise representation of state sets. A decisive factor for this method's success is the chosen variable ordering. Generally speaking, it is plausible that dependent variables should be brought close together in order to reduce BDD sizes. In planning, variable dependencies are typically captured by means of causal graphs, and in preceding work these were taken as the basis for finding BDD variable orderings. Starting from the observation that the two concepts of "dependency" are actually quite different, we introduce a framework for assessing the strength of variable ordering heuristics in sub-classes of planning. It turns out that, even for extremely simple planning tasks, causal graph based variable orders may be exponentially worse than optimal. Experimental results on a wide range of variable ordering variants corroborate our theoretical findings. Furthermore, we show that dynamic reordering is much more effective at reducing BDD size, but it is not cost-effective due to a prohibitive runtime overhead. We exhibit the potential of middle-ground techniques, running dynamic reordering until simple stopping criteria hold.

Cryptographic properties of the hidden weighted bit function

The hidden weighted bit function (HWBF), introduced by R. Bryant in IEEE Trans. Comp. 40 and revisited by D. Knuth in Vol. 4 of The Art of Computer Programming, is a function that seems to be the simplest one with exponential Binary Decision Diagram (BDD) size. This property is interesting from a cryptographic viewpoint since BDD-based attacks are receiving more attention in the cryptographic community. But, to be usable in stream ciphers, the functions must also satisfy all the other main criteria. In this paper, we investigate the cryptographic properties of the HWBF and prove that it is balanced, with optimum algebraic degree and satisfies the strict avalanche criterion. We calculate its exact nonlinearity and give a lower bound on its algebraic immunity. Moreover, we investigate its normality and its resistance against fast algebraic attacks. The HWBF is simple, can be implemented efficiently, has a high BDD size and rather good cryptographic properties, if we take into account that its number of variables can be much larger than for other functions with the same implementation efficiency. Therefore, the HWBF is a good candidate for being used in real ciphers. Indeed, contrary to the case of symmetric functions, which allow such fast implementation but also offer to the attacker some specific possibilities due to their symmetry, its structure is not suspected to be related to such dedicated attacks.

Concatenations of the hidden weighted bit function and their cryptographic properties

To resist Binary Decision Diagrams (BDD) based attacks, a Boolean function should have a high BDD size. The hidden weighted bit function (HWBF), introduced by Bryant in 1991, seems to be the simplest function with exponential BDD size. In [28], Wang et al. investigated the cryptographic properties of the HWBF and found that it is a very good candidate for being used in real ciphers. In this paper, we modify the HWBF and construct two classes of functions with very good cryptographic properties (better than the HWBF). The new functions are balanced, with almost optimum algebraic degree and satisfy the strict avalanche criterion. Their nonlinearity is higher than that of the HWBF. We investigate their algebraic immunity, BDD size and their resistance against fast algebraic attacks, which seem to be better than those of the HWBF too. The new functions are simple, can be implemented efficiently, have high BDD sizes and rather good cryptographic properties. Therefore, they might be excellent candidates for constructions of real-life ciphers.

Can we trust module-respect heuristics?

BDD (Binary Decision Diagrams) have proven to be a very efficient tool to assess Fault Trees. However, the size of BDD, and therefore the efficiency of the whole methodology, depends dramatically on the choice of variable ordering. The determination of the best variable ordering is intractable. Therefore, heuristics have been designed to select reasonably good variable orderings. One very important common feature for good static heuristics is to respect modules. In this paper, the notion of module-respect is studied in a systematic way. It is proved that under certain condition there always exists an optimal ordering that respects modules. This condition is that for each module there is always a smallest module BDD and each included module variable appears only once. On the other hand, it is shown that for the trees not satisfying the above sufficient condition the optimal orderings may not be able to be directly generated using module-respect heuristics, even when the shuffling strategy is used.

NEW RESULTS TO BDD TRUNCATION METHOD FOR EFFICIENT TOP EVENT PROBABILITY CALCULATION

A Binary Decision Diagram (BDD) is a graph-based data structure that calculates an exact top event probability (TEP). It has been a very difficult task to develop an efficient BDD algorithm that can solve a large problem since its memory consumption is very high. Recently, in order to solve a large reliability problem within limited computational resources, Jung presented an efficient method to maintain a small BDD size by a BDD truncation during a BDD calculation. In this paper, it is first identified that Jung’s BDD truncation algorithm can be improved for a more practical use. Then, a more efficient truncation algorithm is proposed in this paper, which can generate truncated BDD with smaller size and approximate TEP with smaller truncation error. Empirical results showed this new algorithm uses slightly less running time and slightly more storage usage than Jung’s algorithm. It was also found, that designing a truncation algorithm with ideal features for every possible fault tree is very difficult, if not impossible. The so-called ideal features of this paper would be that with the decrease of truncation limits, the size of truncated BDD converges to the size of exact BDD, but should never be larger than exact BDD.

Counterexamples to the long-standing conjecture on the complexity of BDD binary operations

In this article, we disprove the long-standing conjecture, proposed by R.E. Bryant in 1986, that his binary decision diagram (BDD) algorithm computes any binary operation on two Boolean functions in linear time in the input–output sizes. We present Boolean functions for which the time required by Bryantʼs algorithm is a quadratic of the input–output sizes for all nontrivial binary operations, such as ∧, ∨, and ⊕. For the operations ∧ and ∨, we show an even stronger counterexample where the output BDD size is constant, but the computation time is still a quadratic of the input BDD size. In addition, we present experimental results to support our theoretical observations.

BDD based construction of resilient functions

The construction of modern cryptographic systems relies on the so-called resilient Boolean functions, a special class of Boolean functions that possesses a balance between a high level of nonlinearity and correlation immunity. In this paper, we discuss the problem of the compact representation and efficient construction of resilient functions. Binary Decision Diagrams (BDDs) were extensively used as a method of compact representation of various classes of Boolean functions. Furthermore, BDDs offer an opportunity for the efficient implementation of different construction methods for resilient functions. In this paper, we make use of BDDs with attributed edges to provide an implementation of two construction methods proposed by Maitra and Sakar. In addition, we demonstrate that the size of BDDs of resilient functions obtained in this way grows linearly with the number of variables.

Cultural algorithm for minimization of binary decision diagram and its application in crosstalk fault detection

The binary decision diagrams (BDDs) can give canonical representation to Boolean functions; they have wide applications in the design and verification of digital systems. A new method based on cultural algorithms for minimizing the size of BDDs is presented in this paper. First of all, the coding of an individual representing a BDDs is given, and the fitness of an individual is defined. The population is built by a set of the individuals. Second, the implementations based on cultural algorithms for the minimization of BDDs, i.e., the designs of belief space and population space, and the designs of acceptance function and influence function, are given in detail. Third, the fault detection approaches using BDDs for digital circuits are studied. A new method for the detection of crosstalk faults by using BDDs is presented. Experimental results on a number of digital circuits show that the BDDs with small number of nodes can be obtained by the method proposed in this paper, and all test vectors of a fault in digital circuits can also be produced.

High Accuracy Asymptotic Bounds on the BDD Size and Weight of the Hardest Functions

In this paper we study the representation of Boolean functions by general binary decision diagrams (BDDs). We investigate the size L(Σ) (number of inner nodes) of BDD Σ with different constraints on the number M(Σ) of its merged nodes. Furthermore, we introduce a weighted complexity measure W(Σ) = L(Σ) + ωM(Σ), where ω > 0. For the hardest Boolean function on n input variables we define the weight WBDD(n) and the size LBDD(n,t), where t limits the number of merged nodes. By using a new synthesis method and appropriate restrictions for the number t of merged nodes, we are able to prove tight upper and lower asymptotic bounds: WBDD(n) = 2n/n (1 + log n ± O(1)/n), LBDD(n,t) = 2n/log nt (1 ± O(1/n)), which have a relative error of O(1/n). Our results show how weight and structural restrictions of general BDDs influence the complexity of the hardest function in terms of high accuracy asymptotic bounds.

Propositionalizing the EM algorithm by BDDs

We propose an Expectation-Maximization (EM) algorithm which works on binary decision diagrams (BDDs). The proposed algorithm, BDD-EM algorithm, opens a way to apply BDDs to statistical learning. The BDD-EM algorithm makes it possible to learn probabilities in statistical models described by Boolean formulas, and the time complexity is proportional to the size of BDDs representing them. We apply the BDD-EM algorithm to prediction of intermittent errors in logic circuits and demonstrate that it can identify error gates in a 3bit adder circuit.