Binary Decision Diagram Technique Research Articles

A hybrid approach of partially applying BDD for seismic PSA quantification

The binary decision diagram (BDD) method provides a means to calculate the exact probability of a fault tree, but cannot solve large fault trees for nuclear power plant PSAs. However, the BDD method can be used as a supplementary means to increase the accuracy of PSA quantification, especially for a seismic PSA which includes many non-rare events.Since it is difficult to solve a large PSA model using BDD method, several approaches have been developed that partially apply the BDD technique to small-sized branches of a large PSA model. This paper proposes an approach of partially applying BDD technique to large-sized branches. The results from the pilot application to a seismic PSA model shows that the partial BDD approach of this paper provides a relatively accurate way to quantify each sequence as well as the overall core damage in a seismic PSA model.

A survey on binary decision diagram approaches to symbolic analysis of analog integrated circuits

Applying symbolic techniques for analog circuit analysis is a traditional research subject, which has lasted for over half a century. The past decade has witnessed a significant advancement of the symbolic techniques developed specifically for large analog integrated circuits. The key methodology introduced is a data structure called binary decision diagram (BDD) which was established originally for logic design and verification. The application of the BDD technique for analog circuit analysis has the following features: (1) It is a compact data structure so that data redundancy in symbolic analysis can be eliminated. (2) It provides a mechanism for implicit enumeration method so that exhaustive enumeration commonly performed in symbolic analysis can be avoided. (3) Numerical evaluation on a BDD can be made extremely efficient, making it an excellent means for repetitive analysis. More advanced features are yet to be explored. This survey brings together the significant research results published in the past decade and provides a tutorial overview on the basic principles of applying BDD to analog circuit analysis. Some new directions that are potentially valuable for developing future analog design automation tools are discussed and a design example is given to illustrate the application of symbolic techniques.

A Generalized Complementary Intersection Method (GCIM) for System Reliability Analysis

This paper presents a Generalized Complementary Intersection Method (GCIM) that can predict system reliability for series, parallel, and mixed systems. The GCIM is an extension of the original study, referred to as the Complementary Intersection Method (CIM). The CIM was developed to assess system reliability for series systems. The contribution of this paper is to generalize the original CIM so that it can be used for system reliability analysis regardless of system structures (series, parallel, and mixed system). First, we derive a closed-form system reliability formula for a parallel system through its transformation into a series system using De Morgan’s law. Second, a unified system reliability analysis framework is proposed for mixed systems by defining a new System Structure matrix (SS-matrix) and employing the Binary Decision Diagram (BDD) technique. The SS-matrix is used to present any system structure in a comprehensive matrix form. Then the BDD technique together with the SS-matrix automates the process to identify system’s mutually exclusive path sets, of which each path set is a series system. As a result, system reliability with any system structure can be decomposed into the probabilities of the mutually exclusive path sets. Five engineering examples are used to demonstrate that the proposed GCIM can assess system reliability regardless of the system structures.

Combining different binary decision diagram techniques for solving models with multiple failure states

This article explains information flow diagrams (IFDs) in great detail. With these models, scenarios leading to dangerous failures as well as spurious shutdowns can be generated, taking into account several failure modes for basic components. These scenarios can be evaluated in a qualitative and quantified way. For an efficient solution different BDD-techniques were combined, mainly zero suppressed BDDs and binary expression diagrams. It is shown how these techniques were used for the model and how a large BDD is created by assembling several smaller diagrams, so that even large and complex systems can be described and evaluated in a compact and efficient way.

Calculating the Failure Intensity of a Non‐coherent Fault Tree Using the BDD Technique

AbstractThis paper considers a technique for calculating the unconditional failure intensity of any given non‐coherent fault tree. Conventional fault tree analysis (FTA) techniques involve the evaluation of lengthy series expansions and approximations are unavoidable even for moderate sized fault trees. The binary decision diagram (BDD) technique overcomes some of the shortfalls of conventional FTA techniques enabling efficient and exact quantitative analysis of both coherent and non‐coherent fault trees. Copyright © 2004 John Wiley & Sons, Ltd.

Comparison of two new approaches to variable ordering for binary decision diagrams

AbstractFault tree analysis, FTA, is one of the most commonly used techniques for safety system analysis. There can be problems with the efficiency and accuracy of the approach when dealing with large tree structures. Recently the binary decision diagram (BDD) methodology has been introduced which significantly aids the analysis of the fault tree diagram. The approach has been shown to improve both the efficiency of determining the minimal cut sets of the fault tree, and also the accuracy of the calculation procedure used to quantify the top event parameters.To utilize the BDD technique the fault tree structure needs to be converted into the BDD format. Converting the fault tree is relatively straightforward but requires the basic events of the tree to be placed in an ordering. The ordering of the basic events is critical to the resulting size of the BDD, and ultimately affects the performance and benefits of this technique. There are a number of variable ordering heuristics in the literature, however the performance of each depends on the tree structure being analysed. These heuristic approaches do not yield a minimal BDD structure for all trees, some approaches generate orderings that are better for some trees but worse for others.Within this paper two approaches to the variable ordering problem have been discussed. The first is the pattern recognition approach of neural networks, which is used to select the best ordering heuristic for a given fault tree from a set of alternatives. The second examines a completely new heuristic approach of using the structural importance of a component to produce a ranked ordering. The merits of each are discussed and the results compared. Copyright © 2001 John Wiley & Sons, Ltd.