Binary Bose-Chaudhuri-Hocquenghem Research Articles

The Discrete Fourier Transform Over the Binary Finite Field

The novel methods for binary discrete Fourier transform (DFT) computation over the finite field have been proposed. The methods are based on a binary trace calculation over the finite field and use the cyclotomic DFT. The direct DFT computational complexity has been reduced due to using the binary trace function over the finite field and the functions of trace which are stored in small tables. The computational complexity of the inverse DFT has been reduced due to representation of elements in the finite field with respect to the normal basis. The proposed methods can be used for encoding/decoding subfield subcodes, especially for binary Bose–Chaudhuri–Hocquenghem (BCH) codes. The computational complexity of the direct/inverse DFT computation methods is the smallest of all known methods.

Analysis of Blind Reconstruction of BCH Codes.

In this paper, the theoretical lower-bound on the success probability of blind reconstruction of Bose–Chaudhuri–Hocquenghem (BCH) codes is derived. In particular, the blind reconstruction method of BCH codes based on the consecutive roots of generator polynomials is mainly analyzed because this method shows the best blind reconstruction performance. In order to derive a performance lower-bound, the theoretical analysis of BCH codes on the aspects of blind reconstruction is performed. Furthermore, the analysis results can be applied not only to the binary BCH codes but also to the non-binary BCH codes including Reed–Solomon (RS) codes. By comparing the derived lower-bound with the simulation results, it is confirmed that the success probability of the blind reconstruction of BCH codes based on the consecutive roots of generator polynomials is well bounded by the proposed lower-bound.

Blind recognition of binary BCH codes based on Euclidean algorithm

A novel method based on Euclidean algorithm is proposed to solve the problem of blind recognition of binary Bose–Chaudhuri–Hocquenghem (BCH) codes in non-cooperative applications. By carrying out iterative Euclidean divisions on the demodulator output bit-stream, the proposed method can determine the codeword length and generator polynomial of unknown BCH code. The computational complexity is derived as O (n 3 ). Simulation results show the efficiency of the proposed method.

VLSI Architectures for Reed–Solomon Codes: Classic, Nested, Coupled, and Beyond

Classic Reed-Solomon (RS) codes and binary Bose-Chaudhuri-Hocquenghem (BCH) codes, which can be considered as a special case of RS codes, are utilized for error correction in numerous systems, such as Flash memories, optical communications, wireless communications, magnetic storage, and deep-space probing. Additionally, RS and BCH codes are interleaved/nested to form high-gain coding schemes, including product and product-like codes and the recent generalized integrated interleaved codes, which are among the most promising candidates to address the hyper-speed and excellent-correction-capability requirements posed by next-generation terabit/s digital communications and storage. In recent developments, RS codes are also split/nested/coupled to form locally recoverable erasure codes and minimum storage regenerating codes that substantially improve the efficiency of failure recovery and enable the continued scaling of large-scale distributed storage. In this article, prominent decoder architectures for classic RS/BCH codes are elaborated and the fundamental mathematical reformulations leading to the architectures are explained. Then the challenges and recent advancements on the decoder design of nested RS/BCH codes are highlighted. Erasure-correcting RS decoders for failure recovery are also briefly discussed. The goal of this article is to provide comprehensive understanding of state-of-the-art VLSI architectures for classic RS/BCH codes and introduce the most recent architectures for new coding schemes built by nesting/coupling RS/BCH codes for emerging applications.

Soft‐input bit‐flipping decoding of generalised concatenated codes for application in non‐volatile flash memories

Error correction coding based on soft-input decoding can significantly improve the reliability of non-volatile flash memories. This work proposes a soft-input decoder for generalised concatenated (GC) codes. GC codes are well suited for error correction in flash memories for high reliability data storage. The authors propose GC codes constructed from inner extended binary Bose–Chaudhuri–Hocquenghem (BCH) codes and outer Reed–Solomon (RS) codes. The extended BCH codes enable an efficient hard-input decoding. Furthermore, a low-complexity soft-input decoding method is proposed. This bit-flipping decoder uses a fixed number of test patterns and an algebraic decoder for soft-decoding. An acceptance criterion for the final candidate codeword is proposed. Combined with error and erasure decoding of the outer RS codes, this acceptance criterion can improve the decoding performance and reduce the decoding complexity. The presented simulation results show that the proposed bit-flipping decoder in combination with outer error and erasure decoding can outperform maximum-likelihood decoding of the inner codes.

Some binary BCH codes with length n = 2m + 1

Under research for nearly sixty years, Bose–Chaudhuri–Hocquenghem (BCH) codes have played increasingly important roles in many applications such as communication, data storage and information security. However, the dimension and minimum distance of BCH codes have been seldom solved by now because of their intractable characteristics. The objective of this paper is to study the dimensions of some binary BCH codes with length n=2m+1. Many new techniques are employed to investigate the coset leaders modulo n. For m=2t+1,4t+2,8t+4 and m≥10, the first five largest coset leaders modulo n are determined, and the dimensions of some BCH codes of length n with designed distance δ>2⌈m2⌉ are presented. These new skills and results may be helpful to study other types of cyclic codes over finite fields.

Soft input decoder for high‐rate generalised concatenated codes

Generalised concatenated (GC) codes are well suited for error correction in flash memories for high-reliability data storage. The GC codes are constructed from inner extended binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer Reed-Solomon codes. The extended BCH codes enable high-rate GC codes and low-complexity soft input decoding. This work proposes a decoder architecture for high-rate GC codes. For such codes, outer error and erasure decoding are mandatory. A pipelined decoder architecture is proposed that achieves a high data throughput with hard input decoding. In addition, a low-complexity soft input decoder is proposed. This soft decoding approach combines a bit-flipping strategy with algebraic decoding. The decoder components for the hard input decoding can be utilised which reduces the overhead for the soft input decoding. Nevertheless, the soft input decoding achieves a significant coding gain compared with hard input decoding.

Generalized Integrated Interleaved Codes

Generalized integrated interleaved codes refer to two-level Reed-Solomon codes, such that each code of the nested layer belongs to different subcode of the first-layer code. In this paper, we first devise an efficient decoding algorithm by ignoring first-layer miscorrection and by intelligently reusing preceding results during each iteration of a decoding attempt. Neglecting first-layer miscorrection also enables to explicitly and neatly formulate the decoding failure probability. We next derive an erasure correcting algorithm for redundant arrays of independent disks systems. We further construct an algebraic systematic encoding algorithm, which had been open. Analogously, we propose a novel generalized integrated interleaving scheme over binary Bose-Chaudhuri–Hocquenghem codes, reveal a lower bound on the minimum distance, and derive a similar encoding and decoding algorithm as those of Reed-Solomon codes.

A Soft Input Decoding Algorithm for Generalized Concatenated Codes

This paper proposes a soft input decoding algorithm and a decoder architecture for generalized concatenated (GC) codes. The GC codes are constructed from inner nested binary Bose–Chaudhuri–Hocquenghem (BCH) codes and outer Reed–Solomon codes. In order to enable soft input decoding for the inner BCH block codes, a sequential stack decoding algorithm is used. Ordinary stack decoding of binary block codes requires the complete trellis of the code. In this paper, a representation of the block codes based on the trellises of supercodes is proposed in order to reduce the memory requirements for the representation of the BCH codes. This enables an efficient hardware implementation. The results for the decoding performance of the overall GC code are presented. Furthermore, a hardware architecture of the GC decoder is proposed. The proposed decoder is well suited for applications that require very low residual error rates.

Low-complexity BCH codes with optimized interleavers for DQPSK systems with laser phase noise

The presence of high phase noise in addition to additive white Gaussian noise in coherent optical systems affects the performance of forward error correction (FEC) schemes. In this paper, we propose a simple scheme for such systems, using block interleavers and binary Bose---Chaudhuri---Hocquenghem (BCH) codes. The block interleavers are specifically optimized for differential quadrature phase shift keying modulation. We propose a method for selecting BCH codes that, together with the interleavers, achieve a target post-FEC bit error rate (BER). This combination of interleavers and BCH codes has very low implementation complexity. In addition, our approach is straightforward, requiring only short pre-FEC simulations to parameterize a model, based on which we select codes analytically. We aim to correct a pre-FEC BER of around $$10^{-3}$$10-3. We evaluate the accuracy of our approach using numerical simulations. For a target post-FEC BER of $$10^{-6}$$10-6, codes selected using our method result in BERs around 3$$\times $$× target and achieve the target with around 0.2 dB extra signal-to-noise ratio.

Blind Recognition of Binary BCH Codes for Cognitive Radios

A novel algorithm of blind recognition of Bose-Chaudhuri-Hocquenghem (BCH) codes is proposed to solve the problem of Adaptive Coding and Modulation (ACM) in cognitive radio systems. The recognition algorithm is based on soft decision situations. The code length is firstly estimated by comparing the Log-Likelihood Ratios (LLRs) of the syndromes, which are obtained according to the minimum binary parity check matrixes of different primitive polynomials. After that, by comparing the LLRs of different minimum polynomials, the code roots and generator polynomial are reconstructed. When comparing with some previous approaches, our algorithm yields better performance even on very low Signal-Noise-Ratios (SNRs) with lower calculation complexity. Simulation results show the efficiency of the proposed algorithm.

Decoder architecture for generalised concatenated codes

This paper proposes a pipelined decoder architecture for generalised concatenated (GC) codes. These codes are constructed from inner binary Bose–Chaudhuri–Hocquenghem (BCH) and outer Reed–Solomon codes. The decoding of the component codes is based on hard decision syndrome decoding algorithms. The concatenated code consists of several small BCH codes. This enables a hardware architecture where the decoding of the component codes is pipelined. A hardware implementation of a GC decoder is presented and the cell area, cycle counts as well as the timing constraints are investigated. The results are compared to a decoder for long BCH codes with similar error correction performance. In comparison, the pipelined GC decoder achieves a higher throughput and has lower area consumption.

Interleavers and BCH Codes for Coherent DQPSK Systems With Laser Phase Noise

The relatively high phase noise of coherent optical systems poses unique challenges for forward error correction (FEC). In this letter, we propose a novel semianalytical method for selecting combinations of interleaver lengths and binary Bose-Chaudhuri-Hocquenghem (BCH) codes that meet a target post-FEC bit error rate (BER). Our method requires only short pre-FEC simulations, based on which we design interleavers and codes analytically. It is applicable to pre-FEC BER $\sim 10^{-3}$ , and any post-FEC BER. In addition, we show that there is a tradeoff between code overhead and interleaver delay. Finally, for a target of $10^{-5}$ , numerical simulations show that interleaver-code combinations selected using our method have post-FEC BER around $2\times $ target. The target BER is achieved with 0.1 dB extra signal-to-noise ratio.

Dimensioning BCH Codes for Coherent DQPSK Systems With Laser Phase Noise and Cycle Slips

Forward error correction (FEC) plays a vital role in coherent optical systems employing multi-level modulation. However, much of coding theory assumes that additive white Gaussian noise (AWGN) is dominant, whereas coherent optical systems have significant phase noise (PN) in addition to AWGN. This changes the error statistics and impacts FEC performance. In this paper, we propose a novel semianalytical method for dimensioning binary Bose-Chaudhuri-Hocquenghem (BCH) codes for systems with PN. Our method involves extracting statistics from pre-FEC bit error rate (BER) simulations. We use these statistics to parameterize a bivariate binomial model that describes the distribution of bit errors. In this way, we relate pre-FEC statistics to post-FEC BER and BCH codes. Our method is applicable to pre-FEC BER around 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> and any post-FEC BER. Using numerical simulations, we evaluate the accuracy of our approach for a target post-FEC BER of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> . Codes dimensioned with our bivariate binomial model meet the target within 0.2-dB signal-to-noise ratio.

A CONFIGURABLE BOSE–CHAUDHURI–HOCQUENGHEM CODEC ARCHITECTURE FOR FLASH CONTROLLER APPLICATIONS

Error correction coding (ECC) has become one of the most important tasks of flash memory controllers. The gate count of the ECC unit is taking up a significant share of the overall logic. Scaling the ECC strength to the growing error correction requirements has become increasingly difficult when considering cost and area limitations. This work presents a configurable encoding and decoding architecture for binary Bose–Chaudhuri–Hocquenghem (BCH) codes. The proposed concept supports a wide range of code rates and facilitates a trade-off between throughput and space complexity. Commonly, hardware implementations for BCH decoding perform many Galois field multiplications in parallel. We propose a new decoding technique that uses different parallelization degrees depending on the actual number of errors. This approach significantly reduces the number of required multipliers, where the average number of decoding cycles is even smaller than with a fully parallel implementation.

Information-Dispersion-Entropy-Based Blind Recognition of Binary BCH Codes in Soft Decision Situations

A method of blind recognition of the coding parameters for binary Bose-Chaudhuri-Hocquenghem (BCH) codes is proposed in this paper. We consider an intelligent communication receiver which can blindly recognize the coding parameters of the received data stream. The only knowledge is that the stream is encoded using binary BCH codes, while the coding parameters are unknown. The problem can be addressed on the context of the non-cooperative communications or adaptive coding and modulations (ACM) for cognitive radio networks. The recognition processing includes two major procedures: code length estimation and generator polynomial reconstruction. A hard decision method has been proposed in a previous literature. In this paper we propose the recognition approach in soft decision situations with Binary-Phase-Shift-Key modulations and Additive-White-Gaussian-Noise (AWGN) channels. The code length is estimated by maximizing the root information dispersion entropy function. And then we search for the code roots to reconstruct the primitive and generator polynomials. By utilizing the soft output of the channel, the recognition performance is improved and the simulations show the efficiency of the proposed algorithm.

Optimizing Chien Search Usage in the BCH Decoder for High Error Rate Transmission

In hybrid automatic repeat request (HARQ), Bose-Chaudhuri-Hocquenghem (BCH) coders can be used before transmission over noisy channel. A sent message is retrieved correctly via decoding, whenever it is correctable. For uncorrectable message, a retransmission is requested by the receiver. In this paper, the detection time for uncorrectable words is reduced. In particular, Chien search usage is optimized. It is only used when all roots of the error locator polynomial belong to F_{2^m}^* = GF(2^m) {0}. Two binary primitive narrow sense BCH codes are considered; the short length BCH(63,39,9) and the long length BCH(16383,16215,25) codes.

Fast Chase Decoding Algorithms and Architectures for Reed–Solomon Codes

Chase decoding is a prevalent soft-decision decoding method for algebraic codes where an efficient bounded-distance decoder is available. Essentially, it repeatedly applies bounded-distance decoding upon combinatorially flipping certain least reliable bits (or patterns for nonbinary case). In this paper, we devise a one-pass Chase decoding algorithm of Reed-Solomon codes such that the desired error locator polynomial by flipping an error pattern is obtained in one pass (when operated in parallel) through utilizing the preceding results. This is effectively achieved through cumulative interpolation and linear-feedback-shift-register (LFSR) synthesis techniques. Furthermore, through converting the algorithm into the transform domain, exhaustive root search for each error locator polynomial is circumvented. Computationally, the new algorithm exhibits linear complexity , in attempting to determine a candidate codeword associated with each additionally flipped symbol/pattern; it compares favorably to quadratic complexity by straightforwardly utilizing hard-decision decoding, where and denote the code length and minimum distance, respectively. We also reveal a corrected algorithm for one-pass generalized minimum distance (GMD) decoding for Reed-Solomon codes from Koetter's original work. In addition, we devise a highly efficient one-pass Chase decoding algorithm for binary Bose-Chaudhuri-Hocquenghem (BCH) codes by taking advantage of a key characteristic of the Berlekamp algorithm. Finally, we present a systolic very large-scale integration (VLSI) decoder architecture through slightly compromising the proposed one-pass Chase decoding algorithm. It takes clock cycles to complete one iteration by flipping one error pattern. Both circuit and memory complexities are dictated by the dimension of flipping patterns; in particular, they are independent of the code length or the minimum distance , rendering it highly attractive for various applications.

Low Power Chien Search for BCH Decoder Using RT-Level Power Management

As a major contributor to the Bose-Chaudhuri-Hocquenghem (BCH) decoder's power consumption, Chien search is a critical step in the binary BCH decoding process for many portable applications. This paper proposes a new low-power design strategy by applying register transfer level (RTL) power management with significant power savings. The proposed Chien search is implemented for a (255, 187, 9) code in CMOS 0.18-μm technology, and simulations show 34% power improvement over the conventional method.

Multibit Error-Correction Methods for Latency-Constrained Flash Memory Systems

This paper presents multibit error-correction schemes for nor Flash used specifically for execute-in-place applications. As architectures advance to accommodate more bits/cell and geometries decrease to structures that are smaller than 32 nm, single-bit error-correction codes (ECCs) are unable to compensate for the increasing array bit error rates, making it imperative to use 2-b ECC. However, 2-b ECC algorithms are complex and add a timing overhead on the memory read access time. This paper proposes low-latency multibit ECC schemes. Starting with the binary Bose-Chaudhuri-Hocquenghem (BCH) codes, an optimized scheme is introduced which combines a multibit error-correcting BCH code with Hamming codes in a hierarchical manner to give an average latency as low as that of the single-bit correcting Hamming decoder. A Hamming algorithm with 2-b error-correcting capacity for very small block sizes (< 1 B) is another low-latency multibit ECC algorithm that is discussed. The viability of these methods and algorithms with respect to latency and die area is proved vis-a¿-vis software and hardware implementations.