Bilayer pseudoSpin Field-Effect Transistor Research Articles

Two-dimensional materials for electronic applications

Abstract

Invited Presentation: The Bilayer Pseudo-Spin Field-Effect Transistor: Overview and Quantum Transport Simulation

The Bilayer pseudo-Spin Field Effect Transistor (BiSFET) [1] is a novel device concept that relies on the possibility of room-temperature excitonic (electron-hole) superfluid condensation in two dielectrically-separated graphene layers [2,3] or other two-dimensional material. The BiSFET is intended to enable much lower voltage—at or below the thermal voltage kBT/q ≈ 26 mV at room temperature—and power operation than possible with Complementary Metal Oxide Semiconductor (CMOS) logic [1,2]. The current-voltage (I-V) characteristics of the proposed BiSFETs, however, are also qualitatively much different from those of MOSFETs, so that new ways to perform logic operations and other functions are both required and offered [4]. At the time of writing, the BiSFET remains a novel transistor concept based on novel physics in a novel material system. Such a room-temperature condensate has not been observed (although it is also the case that the expected necessary experimental conditions have not been realized). However, experimental results in mostly III-V semiconductor double quantum well heterostructures have exhibited much of the essential transport physics required, if only at very low temperatures and under high magnetic fields, e.g. [5]. It is the latter requirements only that the use of graphene layers is intended to eliminate [1,2,3].In this presentation, we will provide an overview of essential BiSFET concepts, and then focus on recent work to understand better how such devices would work to understand better their potential value. We will address both inter- and intra-layer transport within the excitonic superfluid condensate system. To this end, we have developed and performed quantum transport simulations that include the non-local interlayer Fock-exchange interaction on which condensate formation is based.Through simulation, we exhibit the predicted transition from nearly short-circuit behavior below a critical current/voltage to nearly open circuit condition for DC interlayer current flow. Specifically, we have found interlayer conductance of approximately three-fourths of the Landauer-Büttiker limit for perfect transmission below the critical voltage. Above the critical voltage, a spontaneous oscillatory behavior is expected instead of a steady-state current, similar to that of the AC Josephson effect but on the THz and above scale here that would be filtered out in practical circuits. Our simulations have confirmed the lack of steady-state solutions above the critical current, and oscillations in the results from iterative calculations, consistent with this expectation. Through simulation, we also have confirmed that the critical voltage varies as a function of the bare/single particle interlayer coupling strength through the interlayer dielectric, and that the critical voltage can be less than the well below the thermal voltage of 26 mV at 300K.In addition to above critical results, we will show how intra-layer biasing produces near perfect interlayer Coulomb drag. Moreover, to date, field-effect gating has been envisioned for the BiSFET, to adjust the strength of the condensate or the effective contact resistance of individual devices to adjust the critical voltage (where only a little adjustment is needed). However, we are also pursuing the possibility of mixing inter-layer and intra-layer biasing to provide current-controlled switching in what could be called a Bilayer pseudoSpin Junction Transistor (BiSJT), which could reduce device-to-device variability and providing alternate circuit schemes.Acknowledgment: This work is supported by the Nanoelectronics Research Initiative (NRI) through the Southwest Academy of Nanoelectronics (SWAN). Supercomputing resources were provided by the Texas Advanced Computing Center (TACC).

Poly(methyl methacrylate) as a self-assembled gate dielectric for graphene field-effect transistors

We investigate poly(methyl methacrylate) (PMMA) as a low thermal budget organic gate dielectric for graphene field effect-transistors (GFETs) based on a simple process flow. We show that high temperature baking steps above the glass transition temperature (∼130 °C) can leave a self-assembled, thin PMMA film on graphene, where we get a gate dielectric almost for “free” without additional atomic layer deposition type steps. Electrical characterization of GFETs with PMMA as a gate dielectric yields a dielectric constant of k = 3.0. GFETs with thinner PMMA dielectrics have a lower dielectric constant due to decreased polarization arising from neutralization of dipoles and charged carriers as baking temperatures increase. The leakage through PMMA gate dielectric increases with decreasing dielectric thickness and increasing electric field. Unlike conventional high-k gate dielectrics, such low-k organic gate dielectrics are potentially attractive for devices such as the proposed Bilayer pseudoSpin Field-Effect Transistor or flexible high speed graphene electronics.

Theory and synthesis of bilayer graphene intercalated with ICl and IBr for low power device applications

Graphene intercalation materials are potentially promising for the implementation of the ultra-low power, excitonic-condensate-based Bilayer pseudoSpin Field-Effect Transistor (BiSFETs) concept, as well as other novel device concepts requiring a graphene interlayer dielectric. Using density functional theory, we study the structural and electronic properties of bilayer graphene intercalated with iodine monochloride (ICl) and iodine monobromide (IBr). We determine the structural configuration of ICl and IBr graphene intercalation compounds (GICs). We also conduct an in-depth exploration of inter-layer electronic coupling, using ab initio calculations. The presence of intercalants dopes the graphene layer. It also reduces, but does not eliminate, the electronic coupling between graphene layers, which may enable BiSFET operation. In addition, we present experimental results for ICl-GIC synthesis and characterization.

Bilayer Pseudo-Spin Field Effect Transistor (BiSFET): Concepts and Critical Issues for Realization

The Bilayer pseudo-spin Field Effect Transistor (BiSET) has been proposed as one means of taking advantage of possible room temperature superfluidity in two graphene layers separated by a thin dielectric. In principle, the switching energy per device could be on the scale of 10 zJ, over two orders of magnitude below estimates for "end-of the roadmap" CMOS transistors. However, achieving both the goal of room temperature superfluidity and harnessing it for low-power switching pose substantial challenges, both theoretical and experimental. In this work we review the basic graphene superfluidity and BiSFET concepts, our current understanding―and limits to that understanding―of the requirements for condensate formation, and how these requirements could impact BiSFET design.

Bilayer PseudoSpin Field Effect Transistor (BiSFET): Concepts and Critical Issues for Realization

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From Coherent States in Adjacent Graphene Layers toward Low-Power Logic Circuits

Colleagues and we recently proposed a new type of transistor, a Bilayer PseudoSpin Field Effect Transistor (BiSFET), based on many-body coherent states in coupled electron and hole layers in graphene. Here we review the basic BiSFET device concept and ongoing efforts to determine how such a device, which would be far from a drop-in replacement for MOSFETs in CMOS logic, could be used for low-power logic operation, and to model the effects of engineerable device parameters on the formation and gating of interlayer coherent state.

Bilayer Pseudospin Field-Effect Transistor: Applications to Boolean Logic

We have recently proposed a new type of bilayer graphene-based transistor for ultralow-power (perhaps 1000 times less compared with CMOS) room-temperature operation, namely, the bilayer pseudospin field-effect transistor (BiSFET). BiSFET operation is based on gated exciton-condensate-enhanced tunneling. Here, we discuss implementation, operation, and predicted power consumption of BiSFET-based Boolean logic gates, including an inverter, an inverter-based nor gate, and a programmable nand/or, as well as a BiSFET-based memory element. The advantages over CMOS in terms of lower voltage and power are discussed.

Transfer of Large-Area Graphene Films for High-Performance Transparent Conductive Electrodes

Graphene, a two-dimensional monolayer of sp(2)-bonded carbon atoms, has been attracting great interest due to its unique transport properties. One of the promising applications of graphene is as a transparent conductive electrode owing to its high optical transmittance and conductivity. In this paper, we report on an improved transfer process of large-area graphene grown on Cu foils by chemical vapor deposition. The transferred graphene films have high electrical conductivity and high optical transmittance that make them suitable for transparent conductive electrode applications. The improved transfer processes will also be of great value for the fabrication of electronic devices such as field effect transistor and bilayer pseudospin field effect transistor devices.

Bilayer PseudoSpin Field-Effect Transistor (BiSFET): A Proposed New Logic Device

We propose a new type of graphene-based transistor intended to allow lower voltage, lower power operation than possible with complementary metal-oxide-semiconductor (CMOS) field-effect transistors. Increased energy efficiency is not only important for its own sake, but is also necessary to allow continued device scaling and the resulting increase in computational power in CMOS-like logic circuits. We describe the basic device structure and physics and predicted current-voltage characteristics. Advantages over CMOS in terms of lower voltage and power are discussed.