BiCMOS Technology Research Articles

A 24–30‐GHz Modified Gilbert‐Cell Downconverter With High Linearity and Isolation

ABSTRACTThis paper introduces a downconverter mixer employing a modified double‐balanced Gilbert‐cell topology, designed using IHP's 0.13‐m SiGe BiCMOS technology. Distinct from the conventional topology, a resonator was employed at the emitter of the transconductance stage, which enables the utilization of transconductance stage as an active balun, allowing for direct feeding of the single‐ended input without sacrificing the advantageous of the double‐balanced topology. The integration of the resonator reduces the amplitude and phase errors within the active balun segment, thereby enhancing port‐to‐port isolation. The area occupied by the resonator is approximately 1.7 times smaller than that of an RF transformer balun typically employed in conventional double‐balanced topologies. The LO and IF differential signals are converted to single‐ended ones through transformer baluns for measurement purposes. The frequencies of operation for RF, LO, and IF are 24–30, 18–24, and 6 GHz, respectively. The conversion loss is 7.7 dB at 26 GHz, with port‐to‐port isolations exceeding 35 dB. The input 1‐dB compression point is 5.7 dBm, while the circuit consumes 65‐mW power from a 3.3‐V voltage supply. Excluding the pads, the active area of the design spans 1 mm2.

A low-power quadrature voltage-controlled oscillators with LC emitter degeneration phase shift technique

This paper introduces a novel phase-shifting technique for quadrature voltage-controlled oscillators (QVCOs) utilizing an LC emitter degeneration architecture. The proposed technique enables a phase shift of up to ±90°in the transconductance of the coupling path while also generating a negative input resistance. This innovative approach avoids phase ambiguity, mitigates the trade-off between phase noise and phase error, and substantially reduces QVCO power consumption. Moreover, compared to conventional capacitance emitter degeneration methods, the LC emitter degeneration structure has a lower equivalent input capacitance, expanding the QVCO’s frequency tuning range. The designed QVCO is implemented using a 180 nm SiGe BiCMOS technology, occupying a compact area of 0.037 mm2. Post-layout simulation evaluations under various process, voltage, and temperature (PVT) conditions validate the robustness and reliability of the design. Results indicate a phase noise of 102.7 dBc/Hz at a 1 MHz offset from a 22.1 GHz carrier, a frequency tuning range of 25.2%, a phase error of 0.9°, and a power consumption of 12 mW from a 1.1 V supply, achieving a figure of merit (FoM) of 178.8 dBc/Hz.

On novel front-end electronics for the ATLAS BI RPC upgrade at HL-LHC developed in SiGe BiCMOS technology with a high-resolution rad-hard Time-To-Digital converter embedded

The High Luminosity phase of LHC will require a huge improvement on the ATLAS detector in terms of performance, being the entire apparatus operated in much harsher conditions. The BI project is one of the ATLAS Phase-2 approved upgrades, ensuring the demands coming from the physics for the next 20 years. In this framework, a novel dedicated Front-End electronics has been developed, which exploits a BJT-based preamplifier, a fast discriminator and a high resolution (¡ 100 ps) Time-To-Digital converter in SiGe BiCMOS technology, to vastly enhance the detector rate capability. This front-end electronics is integrated for the first time within the detector Faraday cage, largely reducing the effects of spurious noise and allowing a minimum effective charge threshold on the induced signal of 1-2 fC. The integration of the front-end electronics directly within the detector Faraday cage is also permitted by the low power consumption of 15 mW/ch. The RPC coupled with this novel front-end electronics represents a new generation of large area timing detectors, granting a record time resolution of 350 ps on a single gas gap of 1 mm with 1.2 mm electrodes thickness and operated with the ATLAS standard gas mixture. The effect of the extremely low threshold has also an impact on the gas mixture, enabling the usage of eco-friendly gas mixtures which would not be usable elsewise. The latest performance of this newly developed front-end electronics along with the results achieved with RPC detector coupled with it will be shown.

Testbeam results of irradiated SiGe BiCMOS monolithic silicon pixel detector without internal gain layer

Samples of the monolithic silicon pixel ASIC prototype produced in 2022 within the framework of the Horizon 2020 MONOLITH ERC Advanced project were irradiated with 70 MeV protons up to a fluence of 1 × 1016 neq/cm2, and then tested using a beam of 120 GeV/c pions. The ASIC contains a matrix of 100 μm pitch hexagonal pixels, read out by low noise and very fast frontend electronics produced in a 130 nm SiGe BiCMOS technology process. The dependence on the proton fluence of the efficiency and the time resolution of this prototype was measured with the frontend electronics operated at a power density between 0.13 and 0.9 W/cm2. The testbeam data show that the detection efficiency of 99.96% measured at sensor bias voltage of 200 V before irradiation becomes 96.2% after a fluence of 1 × 1016 neq/cm2. An increase of the sensor bias voltage to 300 V provides an efficiency to 99.7% at that proton fluence. The timing resolution of 20 ps measured before irradiation rises for a proton fluence of 1 × 1016 neq/cm2 to 53 and 45 ps at HV = 200 and 300 V, respectively.

Cryo-CMOS Multi-Frequency Modulator for 2-Qubit Controller

This paper addresses the design of a CMOS modulator to control two quantum bits. The proposed architecture offers several advantages that are addressed and discussed in this paper. The proposed architecture is investigated through both mathematical modeling and Verilog simulations. Moreover, the circuit was designed using the cryogenic Design Kit of the 130 nm SiGe BiCMOS technology of the IHP foundry. The observed agreement between the modeling, Verilog, and transistor-level simulations proves the physical feasibility of the proposed architecture.

Design of AD Converters in 0.35 µm SiGe BiCMOS Technology for Ultra-Wideband M-Sequence Radar Sensors.

The article presents the analysis, design, and low-cost implementation of application-specific AD converters for M-sequence-based UWB applications to minimize and integrate the whole UWB sensor system. Therefore, the main goal of this article is to integrate the AD converter's own design with the UWB analog part into the system-in-package (SiP) or directly into the system-on-a-chip (SoC), which cannot be implemented with commercial AD converters, or which would be disproportionately expensive. Based on the current and used UWB sensor system requirements, to achieve the maximum possible bandwidth in the proposed semiconductor technology, a parallel converter structure is designed and presented in this article. Moreover, 5-bit and 4-bit parallel flash AD converters were initially designed as part of the research and design of UWB M-sequence radar systems for specific applications, and are briefly introduced in this article. The requirements of the newly proposed specific UWB M-sequence systems were established based on the knowledge gained from these initial designs. After thorough testing and evaluation of the concept of the early proposed AD converters for these specific UWB M-sequence systems, the design of a new AD converter was initiated. After confirming sufficient characteristics based on the requirements of UWB M-sequence systems for specific applications, a 7-bit AD converter in low-cost 0.35 µm SiGe BiCMOS technology from AMS was designed, fabricated, and presented in this article. The proposed 7-bit AD converter achieves the following parameters: ENOB = 6.4 bits, SINAD = 38 dB, SFDR = 42 dBc, INL = ±2-bit LSB, and DNL = ±1.5 LSB. The maximum sampling rate reaches 1.4 Gs/s, the power consumption at 20 Ms/s is 1050 mW, and at 1.4 Gs/s is 1290 mW, with a power supply of -3.3 V.

A rail-to-rail high speed comparator with LVDS output in 0.18-[formula omitted]m SiGe BiCMOS Technology

Achieving low propagation delay in comparators under low input overdrive voltage is challenging. To overcome this difficulty, this paper presents a novel rail-to-rail high-speed comparator. By clamping the output node of the current summation circuit relative to a fixed level VC, the overdrive recovery time under large signal is successfully reduced. Moreover,by adopting a cascaded approach with multiple stages of high bandwidth and low gain,not only is the comparator’s gain enhanced,but it also acquires higher bandwidth. Ultimately, the comparator’s output is transmitted at high speed through an LVDS interface. This design is implemented using 0.18μm SiGe BiCMOS technology. Simulation results show that the comparator has a static power consumption of 26.4 mW, and for 5 mV input overdrive, the average propagation delay is about 1.09 ns.

A 56‐GBaud lumped linear push–pull driver for Mach–Zehnder modulator in 130‐nm SiGe technology

AbstractA fully differential lumped linear driver for Mach–Zehnder modulator has been presented and assessed in 130‐nm SiGe BiCMOS technology. Multitopology peaking techniques, especially T‐coil peaking method, have been employed to flatten the frequency response and increase the bandwidth. Degeneration resistors have been used to enhance circuit linearity. Simultaneously, improvements have been made to the output stage of the conventional single emitter follower push–pull) circuit to enhance the output eye diagram quality at higher transmission rates. The fabricated driver achieved a differential gain of 16.2 dB with a bandwidth of over 50 GHz, corresponding to a fixed output swing of over 3.2 Vppd within the automatic gain control loop. Time domain measurements, limited in speed by the measurement setup, reported a data rate up to 56 Gb/s none return to zero and 40‐GBaud 4‐levels pulse amplitude modulation with a bit error rate less than 10−12.

A High Gain Concurrent Dual-band Low-Noise Amplifier in 130-nm BiCMOS Technology

This paper presents a fully integrated concurrent 15/30-GHz dual-band low-noise amplifier (LNA). The proposed concurrent LNA IC is designed and simulated in 130-nm BiCMOS technology. The new passive LC notch filter is proposed to realize high gain and low noise figure over dual-band frequency, simultaneously. The simulated BiCMOS LNA IC has exhibited peak gains of 30.1/23.7 dB at 15/30-GHz, respectively, with 20-mW power consumption from 1-V supply. The concurrent dual-band LNA achieves noise figure of 2.2/2.9-dB and IIP3 of -18.2/-8.8 dBm at the respective passbands. Therefore, the proposed dual band concurrent LNA IC is applicable to front-end RF receivers for Ku-Band and Ka-Band systems.

Design of Impedance Matching Network for Low-Power, Ultra-Wideband Applications

This paper addresses the design of ultra-wideband (UWB) impedance matching networks operating in the unlicensed 3.1–10.6 GHz frequency band for low-power applications. It improves the simplified real frequency technique (SRFT) by adding a realizability check and employing an iterative approach with different initial guesses in optimization to achieve realizable solutions under the requirements of UWB, low-power consumption, and a minimum number of circuit components. The comparison of solutions obtained using the SRFT with published solutions based on the Chebyshev filter theory is presented. It is shown that the optimal SRFT solution requires fewer components in the impedance matching network, maximizes the RF power delivery over the UWB spectrum with a reflection coefficient below −10 dB, and allows for circuit optimization to reduce power consumption. Using the improved SRFT, it demonstrates a systematic approach to find the strategies and limitations of designing the input matching networks for low-power UWB applications using GlobalFoundries 90 nm BiCMOS technology.

RapidIP — Automated design of a 220–260 GHz power amplifier in a 130 nm BiCMOS technology

In this work, the automated design of a power amplifier circuit in a 130 nm BiCMOS technology operating in the 220 GHz to 260 GHz frequency range is presented. The design automation process is based on the RapidIP approach, which enables the evaluation, rating and optimisation of thousands of different circuit topologies within only a few minutes. In total 6.13⋅105 optimisation steps and 2.6⋅104 different circuit topologies have been explored within an overall runtime of 23 min. According to post-layout simulations, the amplifier achieves a saturated output power of 9 dBm with a peak power-added efficiency of 2.8% and a 3 dB-bandwidth of 55 GHz.

Compact terahertz devices based on silicon in CMOS and BiCMOS technologies

Compact terahertz devices based on silicon in CMOS and BiCMOS technologies

Compact, High-Speed Mach-Zehnder Modulator With On-Chip Linear Drivers in Photonic BiCMOS Technology

Compact, High-Speed Mach-Zehnder Modulator With On-Chip Linear Drivers in Photonic BiCMOS Technology

Waveguide Integration and Packaging of a Multi-Channel Power Amplifier in a SiGe BiCMOS Technology for mm-Wave Applications

Waveguide Integration and Packaging of a Multi-Channel Power Amplifier in a SiGe BiCMOS Technology for mm-Wave Applications

A 4.65 [formula omitted]V/V line regulation, transient enhanced, capacitor-less LDO with ultra-low load current dependence

A capacitor-less low-dropout regulator (CL-LDO) based on an improved flipped voltage follower (FVF) cell with robust regulation capability and high transient response is presented. The line regulation (LNR) and load regulation (LAR) are enhanced by a stable DC operating point design and multiple feedback loops. A nested feed-forward gm-stage and a nulling resistor in the nested Miller compensation (NGRNMC) topology ensures stability in various challenging conditions. The proposed CL-LDO was designed in 0.18μm BiCMOS technology and occupied an area of 0.0582 mm2, with a typical input voltage range of 3.0 V–3.6 V and a load range of 0–100 mA. Post-simulation verification under various process, voltage, and temperature (PVT) conditions confirms the design’s robustness and reliability. The proposed design achieves the best figure of merit (FoM) of 1.69 mV among state-of-the-art designs, accompanied by a LNR of 4.65 μV/V and a LAR of 27.881 nV/mA.

A Low-Power V-Band Radar Transceiver Front-End Chip Using 1.5 V Supply in 130-nm SiGe BiCMOS

Energy-efficient, low-voltage, and low-power millimeter-wave (mm-wave) radars are gaining increasing attention for battery-powered commercial applications. In this article, the design of a low-power <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> -band radar sensor based on a transceiver (TRX) front-end chip using 1.5 V supply in an advanced SiGe BiCMOS technology with 300 GHz <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{f}\textsubscript{T}$</tex-math> </inline-formula> and 500 GHz <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{f}\textsubscript{max}$</tex-math> </inline-formula> is presented. The monostatic front-end chip utilizes low-voltage low-power circuit-level design techniques to achieve measured 9-dBm transmitter (TX) output power and 27-dB receiver (RX) gain with a simulated 3.8-dB noise figure (NF) consuming a total of only 72 mW in continuous mode. The TRX chip is used to build a radar sensor, which is experimentally verified in an anechoic chamber. The low-power sensor achieves a 46-dB dynamic range and a ranging precision better than 3.4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> m measured with a static target at 1 m. Phase measurements using the low-power radar in the continuous-wave (CW) mode demonstrate that submillimeter movements can be tracked, and notably main vital parameters of a human can be determined accurately. Experimental results show that the performance of the proposed low-power TRX front-end chip is very competitive with designs in modern CMOS technologies.

A Synthetic Ultra-Wideband Transceiver for Millimeter-Wave Imaging Applications.

In this work, we present a transceiver front-end in SiGe BiCMOS technology that can provide an ultra-wide bandwidth of 100 GHz at millimeter-wave frequencies. The front-end utilizes an innovative arrangement to efficiently distribute broadband-generated pulses and coherently combine received pulses with minimal loss. This leads to the realization of a fully integrated ultra-high-resolution imaging chip for biomedical applications. We realized an ultra-wide imaging band-width of 100 GHz via the integration of two adjacent disjointed frequency sub-bands of 10-50 GHz and 50-110 GHz. The transceiver front-end is capable of both transmit (TX) and receive (RX) operations. This is a crucial component for a system that can be expanded by repeating a single unit cell in both the horizontal and vertical directions. The imaging elements were designed and fabricated in Global Foundry 130-nm SiGe 8XP process technology.

4-channel, 224Gb/s PAM-4 optical transmitter with group delay compensation in 130-nm BiCMOS technology

4-channel, 224Gb/s PAM-4 optical transmitter with group delay compensation in 130-nm BiCMOS technology

A 1.25-GHz multi-amplitude modulator driver in 0.18 μm SiGe BiCOMOS technology for high speed quantum key distribution.

Quantum key distribution (QKD) research has yielded highly fruitful results and is currently undergoing an industrialization transformation. In QKD systems, electro-optic modulators are typically employed to prepare the required quantum states. While various QKD systems operating at GHz repetition frequency have demonstrated exceptional performance, they predominantly rely on instruments or printed circuit boards to fulfill the driving circuit function of the electro-optic modulator. Consequently, these systems tend to be complex with low integration levels. To address this challenge, we have introduced a modulator driver integrated circuit in 0.18 µm SiGe BiCMOS technology. The circuit can generate multiple-level driving signals with a clock frequency of 1.25GHz and a rising edge of ∼50ps. Each voltage amplitude can be independently adjusted, ensuring the precise preparation of quantum states. The measured signal-to-noise ratio was more than 17 dB, resulting in a low quantum bit error rate of 0.24% in our polarization-encoding system. This work will contribute to the advancement of QKD system integration and promote the industrialization process in this field.

A 42 GHz low phase noise Colpitts VCO in 180-nm SiGe BiCMOS

This paper describes a 39.1 to 42.5 GHz low phase noise Colpitts voltage-controlled oscillator (VCO) using 180-nm SiGe BiCMOS technology. In order to achieve better phase noise, an optimization method related to capacitance ratio is analyzed. Meanwhile, the linearization method is used to achieve a linearized KVCO which is robust to varactor bias variations. The simulated VCO features a tuning range of 8%, low phase noise of –95.3 dBc/Hz at 1 MHz offset, voltage supply of 3.3 V and power consumption of 40 mW, which results in a FOM T of –170 dBc/Hz.