The use of thin layers of amorphous hafnium oxide has been shown to be suitable for the manufacture of Resistive Random Access memories (RRAM). These memories are of great interest because of their simple structure and non-volatile character. In this work, it was studied the performance of the MIM structure that takes part of a 4 kbit memory array based on 1-transistor-1-resistance (1T1R) cells, in terms of memory maps and reading and writing loops. In each cell of the memory, a NMOS transistor is placed in series to a metal-insulator-metal (MIM) resistor formed by a TiN/a-HfO2/Ti/TiN structure. The 8 nm-thick HfO2 layers were grown by Atomic Layer Deposition (ALD); all metal films were deposited by magnetron sputtering. The measurements were carried out on MIM structures identical to those of the memory cell but with a larger area, manufactured on a different region of the chip. A previous study about the reduction of the programming pulse width in order to accomplish fast and low-energy switching operations as well as its influence in terms of endurance and data retention times has been published (Pérez et al. Electronics 9, p. 864, 2020). In addition, Logic-In-Memory (LIM) circuits based on this 4-kb RRAMs arrays have been analyzed in terms of reliability and energy consumption tradeoff (Zanotti et al. IEEE Trans. Electron. Devices 67, 10, p. 4611, 2020).In these MIM structures, the resistance value may decrease due to the creation of oxygen vacancy columns that act as conductive filaments between the two electrodes. This process is reversible and controllable, so that two well-defined states can be established. In addition, it is also possible to access intermediate states if appropriate dc bias waveforms are applied. In fact, by biasing with variable amplitude-triangular voltage signals, cumulative writing and erasing cycles can be performed. To obtain the memory maps, return-to-zero pulses rather than ramp voltages bias have to be used. Accordingly, the samples are biased by a train of square pulses with increasing amplitude; after each pulse the current value under a low bias value is measured. The memory map is built from the current values at 0.1 V measured immediately after applying each programming pulse. To carry out a detailed electrical characterization of these devices becomes essential to shed light on the physical nature of the mechanisms of creation and dissolution of the conducting filament, and ultimately to control the memory states. The controllable multilevel ability of these memory devices, due to their resistance transition in a gradual way, enables them to be used not only in the RAM memory field, but also in neuromorphic circuits based on the artificial synapse.It has been shown in HfO2-based RRAM devices that small signal parameters in a wide range of frequencies also show repetitiveness and intermediate states control, and allow to obtain memory maps testing the device at 0 V dc bias, hence without any static power consumption. (Castán et al. J. Appl. Phys. 124, 152101, 2018).In Fig. 1.a I-V cycles showing SET and RESET states are depicted. The blue-colored cycles are the most stable, whereas the very initial ones (red color) show some instability due to the fact that the filament formation process does not seem to have finished yet, and the last ones (green color) already exhibit aging effects.The memory map in Fig.1.b shows good window width values. SET transition is markedly abrupt compared to RESET transitions, which is much more gradual. This means that the best control can be obtained in the RESET transition.The accuracy of the intermediate current values control between SET and RESET is clearly shown in Figs. 1.c and 1.d. Both write and erase operations are carried out incrementally with a very precise control of the successive states through which the memory passes. The initial state must be well established by driving the memory to a full RESET (write operation) or to a full SET (erase operation). To achieve this, a negative or positive enough voltage, respectively, should be applied to the top electrode (with bottom electrode grounded).Similarly, an accurate control of admittance parameters was achieved during cumulative writing and erasing processes. Memory maps were also plotted for real (conductance, G) and imaginary (capacitance, C) components (Fig. 2).Moreover, endurance measurements made up to 6144 SET-RESET cycles exhibited excellent repetitiveness of current values in both states, as well as admittance parameters stability.To sum up, the electrical properties of these RRAM devices in terms of endurance and intermediate states control make them suitable for neuromorphic computing. Figure 1
Read full abstract
Jun 1, 2024
Yuchen Qian + 4
Open Access