Bias Temperature Instability In MOSFETs Research Articles

Bias Temperature Instability of MOSFETs: Physical Processes, Models, and Prediction

CMOS technology dominates the semiconductor industry, and the reliability of MOSFETs is a key issue. To optimize chip design, trade-offs between reliability, speed, power consumption, and cost must be carried out. This requires modeling and prediction of device instability, and a major source of instability is device aging, where defects gradually build up and eventually cause malfunction of circuits. This paper first gives an overview of the major aging processes and discusses their relative importance as CMOS technology developed. Attentions are then focused on the negative and positive bias temperature instabilities (NBTI and PBTI), mainly based on the early works of the authors. The aim is to present the As-grown-Generation (AG) model, which can be used not only to fit the test data but also to predict long-term BTI at low biases. The model is based on an in-depth understanding of the different types of defects and the experimental separation of their contributions to BTI. The new measurement techniques developed to enable this separation are reviewed. The physical processes responsible for BTI are explored, and the reasons for the failure of the early models in predicting BTI are discussed.

Dependence of the Multi-Component Nature of Bias Temperature Instability in MOSFETs on Oxide and Device Type

Advanced metal-oxide-semiconductor field effect transistors, MOSFETs, have shown increasing sensitivity to microelectronic reliability based degradation phenomena and in particular, to negative bias temperature instability, NBTI. Previously [1] we have reported on a methodology to extract three distinct components of NBTI; recoverable charge, RC (oxide traps which discharge once the gate bias is zero), field recoverable charge, FRC (switching traps which seemingly discharged under positive gate bias), and interface state charge, IS (associated with the breaking of silicon-hydrogen bonds at the interface and do not discharge in an experimental time frame for temperatures below 180° C). Here we will report new results for NBTI for different oxide types and thicknesses and we will expand the methodology to include positive bias temperature instability, PBTI, oxide charging caused by the application of large positive biases. Both NBTI and PBTI will be examined for both p-channel and n-channel MOSFETS for each oxide type and thickness, which requires the measurement to be made in both accumulation and inversion modes.NBTI “Pseudo DC” measurements using the methodology discussed previously [1] have been made at 120° C on p-channel and n-channel MOSFETs to extract the three components of BTI after 1500 s of stress. The stressing bias was chosen so that |Vgs,stress|/tox = 3.25 V/3.4nm in order to keep the approximately the same fields. Measurements of the source – drain current, Ids, were made in the linear regime and the measured Ids variations with stress were converted into threshold voltage shifts, DVth [1]. Measurements were performed on devices fabricated using an IBM proprietary process with gate widths of 5 mm and gate length/oxide thicknesses of 130 nm/3.4nm, 240 nm/6.2 nm, 90 nm/2.4 nm, and 240 nm/6.2 nm (processed with 90 nm technology) with a oxynitride gate. Measurements were also performed on HP devices with gate widths of 10 mm, gate lengths ranging from 350-500 nm and a Si02 oxide thickness of 7 nm.It is worth noting that the sign of the trapped charges of each type depends upon the component being measured. In the case of IS, the sign of the charge can be inferred from the mechanism since dangling bonds are amphoteric. They will take on a charge based on the measurement Vgs, and thus for PMOS devices, the IS have positive trapped charge (negative voltage shift) whilst for NMOS the IS are negatively charged (positive voltage shift). The FRC charge component is always charged by holes and the RC charge is positive (negative voltage shift) except for PBTI in an NMOS. A sample table for the 130nm/3.4nm oxynitrided gate is shown below.The existence of positive charge injection, for a PMOS under PBTI can be explained by realizing that PMOS devices usually have a p-type polysilicon gate electrode. When a positive gate bias is applied, electrons will be drawn to the interface between the gate oxide and the substrate; thus there are no holes present to tunnel into the oxide; however, the same field will drive holes from the poly silicon/oxide interface and this is where the positive charge is coming from under these circumstances.A more puzzling result is that an NMOS under PBTI shows IS creation. Standard models of IS creation involve positive charge which either directly or through a complex process breaks the Si-H bond. These holes can come from the substrate for NBTI, or the polysilicon gate for a PMOS in accumulation, but the mechanism of hole injection for an NMOS undergoing PBTI is unclear.[1] C. Mayberry, D. D. Nguyen, C. Kouhestani, K. E. Kambour, H. P. Hjalmarson and R. A. B. Devine, “Measurement and Identification of Three Contributing Charge Terms in Negative Bias Temperature Instability,” ECS Trans., 50 (4), 223-232 (2012). Acknowledgements D. D. Nguyen and C. Kouhestani are with COSMIAC Kirtland, AFB, New Mexico USA 87117. This material is based on research sponsored by Air Force Research Laboratory (AFRL) under agreement number FA9453-08-2-0259. The U.S. Government is authorized to reproduce and distribute reprints for Governmental purposes notwithstanding any copyright notation thereon. The work performed by K. E. K. was supported by the US Air Force under contract FA9453-08-C-0245 sponsored, monitored, and managed by: United States Air Force Air Force Material Command, Air Force Research Laboratory, Space Vehicles Directorate, Kirtland AFB, NM 87117-5776. Table 1 A matrix showing the threshold voltage shift for the various BTI components and type of charge trapped by each component.

Dependence of the Multi-Component Nature of Bias Temperature Instability in MOSFETs on Oxide and Device Type

We have performed negative and positive bias temperature instability (NBTI and PBTI) measurements on devices having different gate oxide types and thicknesses. The devices used for the study include 130nm and 90 nm oxynitrided gate dielectric bulk Si technology and devices with pure SiO2 gate dielectric. NBTI and PBTI were studied for both p-channel and n-channel MOSFETs for each of the oxide types and thicknesses, this requires the measurements be made in both accumulation and inversion modes. Using “Pseudo DC” measurements at 120 oC on p-channel and n-channel devices, we have extracted at least three distinct components of BTI. We find evidence for the existence of positive charge injection for PMOS under PBTI and more puzzling results for NMOS under PBTI, where unexpected interface state creation was observed.

Effect of plasma process-induced damage on bias temperature instability of MOSFETs

For a surface-channel n-MOSFET and a buried-channel p-MOSFET, the effect of plasma process-induced damage on bias temperature instability (BTI) was investigated. The gate oxide thickness, t ox, of the test MOSFETs was 2.0, 3.0, or 4.5 nm. The shifts of threshold voltage V th and of linear drain current I dlin were measured after applying a BTI stress at a temperature of 125 °C. The measured shifts of V th and I dlin indicate that BTI on ultra-thin gate CMOS devices appears only in the form of SiO 2/Si interface degradation, and that the positive BTI for the n-MOSFET as well as the negative BTI for the p-MOSFET is important for the reliability evaluation of CMOS devices. Because of positive plasma charging to the gate, a protection diode was very efficient at reducing BTI for the p-MOSFET, but it was much less effective for the n-MOSFET.

Positive bias temperature instability in MOSFETs

The positive bias temperature instability (PBTI) of submicron MOSFETs has been investigated. It is found that the PBTI can be as large as the well-known negative bias temperature instability (NBTI). While the NBTI includes both Interface state generation and positive charge formation in the gate oxide, the PBTI only exists in the form of donor-like interface state generation. These donor-like interface states are localized symmetrically near the source and drain junctions and are negligible in the middle of the channel. Their dependence on the stressing electrical field strength and temperature is investigated and an activation energy of 1.23 eV is extracted. The PBTI creation follows the first order kinetics and the final saturation level is fixed by the number of defects available in the device. The experimental results show that the water- and boron-related species are two necessary reactants of the electrochemical reaction leading to the PBTI. Some speculation on the PBTI formation process is included.