Behavioral Simulation Research Articles

Energy-efficient switching scheme based on floating technique for SAR ADC

A high energy-efficiency capacitor switching scheme for successive approximation register (SAR) analog-to-digital converters is proposed in the paper. During the design procedure, the charge characteristic of the floating capacitor and the technique of splitting capacitor ensure zero energy consumption of switching operation. With the reset energy of capacitor arrays taken into account, the proposed switching scheme can achieve 100% less switching energy over the conventional switching scheme. Furthermore, this work also achieves about 50% area reduction with only two reference voltages. The behavioral simulation of the proposed SAR was performed, the maximum differential nonlinearity and maximum integral nonlinearity are 0.451 and 0.452 LSB respectively.

Behavioral Simulation of ISO 18000-6 Type-C Class 1 Gen2 Protocol for RFID UHF Transponder and its Application as Anti-collision Protocol in Interference Case

In RFID systems, the Transponder Protocol usually uses the standard ISO 18000-6 Type-C Class 1 Generation 2, originally developed to communicate with the reader. Since a typical RFID system could be used in a myriad of tasks from product identification to environmental sensing, behavioral software functionality and hardware cost constraints are extremely constricted, principally due to their ¶standard’s requirements.¶ Thus, in this paper, an advanced behavioral simulation of the Tag ID layer of ISO 18000-6 Type-C protocol is proposed with all its states, commands and functionality, a crucial step toward effective design and test. The approach was then successfully applied to collision issues in interference case.

Embedding MATLAB Optimizers in SIMSIDES for the High-Level Design of <inline-formula> <tex-math notation="LaTeX">$\Sigma \Delta$ </tex-math> </inline-formula> Modulators

This brief shows how to combine SIMSIDES, a SIMULINK-based time-domain behavioral simulator, with different optimization engines available in MATLAB for the automated high-level design of sigma-delta ( ${\Sigma \Delta }$ ) modulators. To this purpose, an updated version of SIMSIDES has been developed, which includes a user-friendly interface that links the simulator with the optimizers, and guides designers through the main steps required to set the design variables, constraints and select the most suitable algorithm to maximize the performance of an arbitrary modulator topology for a given set of specifications. Several examples and results of the optimization procedure are shown to illustrate the benefits of the presented tool for the high-level synthesis of ${\Sigma \Delta }$ modulators.

Are they satisfied with land taking? Aspects on procedural fairness, monetary compensation and behavioral simulation in China’s land expropriation story

Farmland expropriation and the associated satisfaction or otherwise of farmers has been receiving increased attention under the background of China's rapid urbanization. We use a literature review to identify specific gaps that need to be filled: (1) where and how the satisfaction of land expropriation comes from? (2) how to effectively measure the level of satisfaction? The evaluation of satisfaction is considered to come from three stages of pre, during and post expropriation. This paper aims to examine two groups of land-taken and land-kept farmers by using the binary nonlinear model, logit and order-Probit regression, blinder-Oaxaca decomposition and Heckman two-step selection as the data analysis method. Two research questions are raised in an extended Institutional Analysis and Development (IAD) framework, including: 1) which factors mostly affect farmer's willingness and satisfaction in the IAD framework? and 2) what is the marginal effect of different factors, especially of the interaction between land compensation standards and the openness and fairness of expropriation procedures? The four main results indicate that, firstly, improvement in the compensation criterion is helpful for improving the level of satisfaction, but does not mean that higher compensation is better, because empirical research indicates that simply increasing the amount of compensation does not significantly increase satisfaction unless the farmers are consulted over the land-acquisition procedures and compensation amounts. Second, the most important aspect for the farmers is how much their income level increases, ‘inequality rather than want is the cause of trouble’ and, in the absence of any consultation, ‘waiting for the right place to sell' in the next round. Third, compensation should be allocated to the farmer instead of the rural collective. Fourth, according to the theories of resource endowment and reference dependence, to explicate the negative effect between the strength and perception of property rights, it is considered that the inter-relationship between land ownership and farmland circulation is uncertain. Whether the influence is positive or negative mostly depends on the strength of the property rights, institutional environment, behavioral cognitive ability and the capability to implement or act.

CFCS calibration circuit design for multi-bit pipelined ADC architectures

Design of high resolution ADCs in scaled CMOS technology is challenging due to increased component mismatch, comparator offset, and finite op-amp gain error. In this work, a commutated feedback capacitor switching calibration technique has been proposed to improve the ENOB and linearity of ADCs with multi-bit pipeline architecture. During normal operation of ADC, the fixed sampling capacitor is swapped in the feedback capacitor. We have distributed the sampling capacitor and swap the feedback capacitor with the sampling capacitor(s) in the MDAC of each pipeline stage ADC. The mismatches of different pipeline stages are concurrently corrected in the digital domain. Proposed technique requires digital calibration circuits and requires no extra calibration phase cycles. The prime objective of this work is to achieve high linearity and ENOB in pipeline architectures with low power consumption. Behavioral simulation of 16-bit 5Ms/s pipeline ADC in UMC 0.18 µm double poly triple metal processes with proposed calibration shows significant improvement in DNL with σ = 0.25% capacitor mismatch with correct 16-bit digital output. The design is implemented using HSPICE simulation. The robustness of the proposed technique has been verified by process, temperature and voltage variation simulations and Monte Carlo analysis.

Practical Harmonic Cancellation Techniques for the On-Chip Implementation of Sinusoidal Signal Generators for Mixed-Signal BIST Applications

Harmonic cancellation strategies have been recently presented as a promising solution for the efficient on-chip implementation of accurate sinusoidal signal generators. Classical harmonic cancellation techniques consist in combining a set of time-shifted and scaled versions of a periodical signal in such a way that some of the harmonic components of the resulting signal are cancelled. This signal manipulation strategy can be easily implemented using digital resources to provide a set of phase-shifted digital square-wave signals and a summing network for scaling and combining the phase-shifted square-waves. A critical aspect in the practical implementation of the harmonic cancellation technique is the stringent accuracy required for the scaling weight ratios between the different phase-shifted signals. Small variations between these weights due to mismatch and process variations will reduce the effectiveness of the technique and increase the magnitude of undesired harmonic components. In this work, different harmonic cancellation strategies are presented and analyzed with the goal of simplifying the practical on-chip implementation of the scaling weights. Statistical behavioral simulations are provided in order to demonstrate the feasibility of the proposed approach.

Wind turbines control system: nonlinear modeling, simulation, two and three time scale approximations, and data validation

In this paper, wind turbines dynamics are considered for nonlinear behavioral modeling and simulation. The modeling part is concerned about the wind turbines exposed to lower range of wind speeds. The nonlinear model considered in this paper is derived from the models published recently. The model then is analyzed through stability, eigenvalues, sensitivity and Simulink verification versus General Electric and NREL models. The paper then introduces analysis and simulations for the wind turbines dynamics approximated to fast–slow (two) time scales and fast–medium–slow (three) time scales. The multiple time scale simulation analysis and results we present are a continuation for our previous work (Eisa et al. in Int J Dyn Control 2017. https://doi.org/10.1007/s40435-017-0356-0 ) that concluded rigorous mathematical analysis for wind turbines dynamics. The paper presents full numerical simulation results for the time scale work. Finally, the paper presents a practical illustration by comparing the modeling work versus other models and real measured data from a wind farm.

Nonlinear analysis of VCO jitter generation using Volterra series

PurposeCharge pump phase locked loops (CPPLLs) are nonlinear systems as a result of the nonlinear behavior of voltage-controlled oscillators (VCO). This paper aims to specify jitter generation of voltage controlled oscillator phase noise in CPPLLs, by considering approximated practical model for VCO.Design/methodology/approachCPPLL, in practice, shows nonlinear behavior, and usually in LC-VCOs, it follows second-degree polynomial function behavior. Therefore, the nonlinear differential equation of the system is obtained which shows the CPPLLs are a nonlinear system with memory, and that Volterra series expansion is useful for such systems.FindingsIn this paper, by considering approximated practical model for VCO, jitter generation of voltage controlled oscillator phase noise in CPPLLs is specified. Behavioral simulation is used to validate the analytical results. The results show a suitable agreement between analytical equations and simulation results.Originality/valueThe proposed method in this paper has two advantages over the conventional design and analysis methods. First, in contrast to an ideal CPPLL, in which the characteristic of the VCO’s output frequency based on the control voltage is linear, in the present paper, a nonlinear behavior was considered for this characteristic in accordance with the real situations. Besides, regarding the simulations in this paper, a behavior similar to the second-degree polynomial was considered, which caused the dependence of the produced jitter’s characteristic corner frequency on the jitter’s amplitude. Second, some new nonlinear differential equations were proposed for the system, which ensured the calculation of the produced jitter of the VCO phase noise in CPPLLs. The presented method is general enough to be used for designing the CPPLL.

Analysis of the impact of interferers on VCO-based continuous time delta-sigma modulators

Analog to digital converters (ADCs) used in receivers, face desired and undesired signals. Undesired signals are located out-of-band (OOB) of interest and are stronger than the desired signal and degrade the performance of the ADCs. Continuous time (CT) delta-sigma modulators (DSMs) can provide inherent anti-aliasing and hence they relax the requirement of the dynamic range. In this paper the behavior of CT-DSMs, utilizing voltage controlled oscillators (VCOs), for receiver applications are studied. The results indicate that, due to the frequency modulation occurring in the VCOs, when interfering signals are applied at the half of the sampling frequency (fs), integer multiples of the carrier frequency (fc) and fc/2,fc/3…, modulation tones appear in the bandwidth of the desired channel. This leads to degradation of the signal to noise and distortion ratio (SNDR). An analytical expression for the output signal of the VCO-based integrator in the presence of the interferers has been derived. In addition, behavioral simulations are done for both cascade of integrators in the feedback structure (CIFB) and cascade of integrators in the feedforward structure (CIFF) as well as multi-stage noise shaping (MASH) structures. It will be discussed how the designer should choose the suitable structure.

Crowd behavior simulation based on shadow obstacle and ORCA models

Crowd behavior simulation has become one of the key support technologies for evacuation drills and safety monitoring. However, complex psychology, personality traits and interactions among individuals increase the challenges of creating realistic crowd behavioral simulations. In this paper, we propose a crowd behavior simulation method to simulate crowd behaviors by combining the shadow obstacle model (SOM) and optimal reciprocal collision avoidance (ORCA) model. First, the SOM is converted to the expected speed, as well as the half plane of ORCA. Then, a manual generation method of SOM is proposed to simulate the crowd behaviors in corners or beside a non-closed wall. Finally, we combine behavior simulation and physical simulation techniques, and propose a velocity-based crowd simulation framework. To test the effectiveness of our proposed method, several simulation methods are implemented in a Unity3D engine-based crowd simulation in subway station environment, and the comparison results demonstrate that our proposed method outperforms force-based simulation methods.

3D visual simulation of individual and crowd behavior in earthquake evacuation

Simulation of behaviors in emergencies is an interesting subject that helps to understand evacuation processes and to give out warnings for contingency plans. Individual and crowd behaviors in the earthquake are different from those under normal circumstances. Panic will spread in the crowd and cause chaos. Without considering emotion, most existing behavioral simulation methods analyze the movement of people from the point of view of mechanics. After summarizing existing studies, a new simulation method is discussed in this paper. First, 3D virtual scenes are constructed with the proposed platform. Second, an individual cognitive architecture, which integrates perception, motivation, behavior, emotion, and personality, is proposed. Typical behaviors are analyzed and individual evacuation animations are realized with data captured by motion capture devices. Quantitative descriptions are presented to describe emotional changes in individual evacuation. Facial expression animation is used to represent individuals’ emotions. Finally, a crowd behavior model is designed on the basis of a social force model. Experiments are carried out to validate the proposed method. Results showed that individuals’ behavior, emotional changes, and crowd aggregation can be well simulated. Users can learn evacuation processes from many angles. The method can be an intuitional approach to safety education and crowd management.

Improving a distributed hydrological model using evapotranspiration‐related boundary conditions as additional constraints in a data‐scarce river basin

AbstractMany hydrological models have been calibrated and validated using hydrographs alone. Because streamflow integrates water fluxes in space, many distributed hydrological models tend to have multiple feasible descriptions of hydrological processes. This equifinality usually leads to substantial prediction uncertainty. In this study, additional constraints—namely, the spatial patterns of long‐term average evapotranspiration (ET), shallow groundwater level, and land cover change—were used to investigate the reduction of equifinality and prediction uncertainty in the Soil and Water Assessment Tool (SWAT) in the Wami River basin in Tanzania. The additional constraints were used in the set‐up, parameter emulation and calibration of the SWAT model termed an improved hydrological model (IHM). The IHM was then compared with a classical hydrological model (CHM) that was also developed using the SWAT model but without additional constraints. In the calibration, the CHM used only the hydrograph, but the IHM used the hydrograph and the spatial pattern of long‐term average ET as an additional constraint. The IHM produced a single, unique behavioural simulation, whereas the CHM produced many behavioural simulations that resulted in prediction uncertainty. The performance of the IHM with respect to the hydrograph was more consistent than that of the CHM, and the former clearly captured the mean behaviour of ET in the river basin. Therefore, we conclude that additional constraints substantially reduce equifinality and prediction uncertainty in a distributed hydrological model.

A low-cost digital-domain foreground calibration for high resolution SAR ADCs

A digital-domain foreground calibration method simultaneously correcting mismatch errors in main capacitive digital to analog converter (CDAC) and “segment error” between main CDAC and sub-CDAC of split-CDAC array in high resolution successive approximation register (SAR) analog-to-digital converter (ADC) is proposed. The actual weight is obtained with the digital-domain weight estimation algorithm. This proposed digital-domain calibration saves silicon area by eliminating the need for a dedicated calibration DAC employed in conventional CDAC mismatch calibration schemes. Behavioral simulation shows the proposed calibration is capable of correcting mismatch errors and “segment error” of split-CDAC array, and improving SNDR from 67.3 dB to 92.8 dB in a prototype 16 bit split-CDAC SAR ADC.

The challenges of modelling phosphorus in a headwater catchment: Applying a ‘limits of acceptability’ uncertainty framework to a water quality model

There is a need to model and predict the transfer of phosphorus (P) from land to water, but this is challenging because of the large number of complex physical and biogeochemical processes involved. This study presents, for the first time, a ‘limits of acceptability’ approach of the Generalized Likelihood Uncertainty Estimation (GLUE) framework to the Soil and Water Assessment Tool (SWAT), in an application to a water quality problem in the Newby Beck catchment (12.5 km2), Cumbria, United Kingdom (UK). Using high frequency outlet data (discharge and P), individual evaluation criteria (limits of acceptability) were assigned to observed discharge and P loads for all evaluation time steps, identifying where the model was performing well/poorly and to infer which processes required improvement in the model structure. Initial limits of acceptability were required to be relaxed by a substantial amount (by factors of between 5.3 and 6.7 on a normalized scale depending on the evaluation criteria used) in order to gain a set of behavioral simulations (1001 and 1016, respectively out of 5,000,000). Of the 39 model parameters tested, the representation of subsurface processes and associated parameters, were consistently shown as critical to the model not meeting the evaluation criteria, irrespective of the chosen evaluation metric. It is therefore concluded that SWAT is not an appropriate model to guide P management in this catchment. This approach highlights the importance of high frequency monitoring data for setting robust model evaluation criteria. It also raises the question as to whether it is possible to have sufficient input data available to drive such models so that we can have confidence in their predictions and their ability to inform catchment management strategies to tackle the problem of diffuse pollution from agriculture.

Decimal multiplication using compressor based-BCD to binary converter

The objective of this work is to implement a scalable decimal to binary converter from 8 to 64 bits (i.e 2-digit to 16-digit) using parallel architecture. The proposed converters, along with binary coded decimal (BCD) adder and binary to BCD converters, are used in parallel implementation of Urdhva Triyakbhyam (UT)-based 32-bit BCD multiplier. To increase the performance, compressor circuits were used in converters and multiplier. The designed hardware circuits were verified by behavioural and post layout simulations. The implementation was carried out using Virtex-6 Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) with 90-nm technology library platforms. The results on FPGA shows that compressor based converters and multipliers produced less amount of propagation delay with a slight increase of hardware resources. In case of ASIC implementation, a compressor based converter delay is equivalent to conventional converter with a slight increase of gate count. However, the reduction of delay is evident in case of compressor based multiplier.

Adaptive Cancellation of Static and Dynamic Mismatch Error in Continuous-Time DACs

Inadvertent but inevitable mismatches among nominally identical unit element 1-bit digital-to-analog converters (DACs) within a multi-bit Nyquist-rate DAC cause both static and dynamic error in the DAC’s continuous-time output waveform. Prior calibration techniques are able to suppress static mismatch error, but have had limited success in suppressing dynamic mismatch error. This paper presents a digital calibration technique that adaptively measures and cancels both static and dynamic mismatch error over the DAC’s first Nyquist band. The technique is capable of either foreground or background operation, and is relatively insensitive to non-ideal circuit behavior. The paper presents a rigorous mathematical analysis of the technique, and demonstrates the results of the paper with both behavioral and transistor-level circuit simulations.

A 24 GHz dual FMCW radar to improve target detection for automotive radar applications

A 24 GHz automotive radar with dual frequency modulated continuous waveform (FMCW) is proposed. By using this modulation waveform, the ghost targets can be avoided, especially in multi-target situations. Thus, the detection ability of radar systems can be significantly improved. In this paper, in order to generate the dual FMCW signal, a dual FMCW modulation control logic (DFMCL) is proposed. This block incorporates a 24 GHz fractional-N phase locked loop (PLL), synthesise 24 GHz modulation waveform. The proposed architecture was designed using 130 nm CMOS process. Two alternative chirps of 12 ms and 6 ms were generated in the coherent processing interval. The modulation bandwidth was 200 MHz. Moreover, a radar transceiver, which consists of 24 GHz dual FMCW generator and monolithic microwave integrated circuits (MMICs), was accomplished. A behavioural simulation was conducted to evaluate the operation of the proposed generator. Then, the transceiver was modelled for testing the detection ability of the automotive radar. The results demonstrated that the proposed scheme has the ability to realise the Dual FMCW waveform for automotive radar systems. Furthermore, the system can avoid the ghost targets in multi-target scenarios.

Research and design of intelligent image recognition mechanism and its application

In this paper, an in-depth study on the recognition mechanism (identification experts) and behavioral function simulation is made, and a design method has been developed -----Image recognition mechanism. The research results and methods are expounded. At the same time, experiments are carried out on the above design methods. The effectiveness and feasibility of this design have been proved by experiments. Furthermore, the design of the expert observer is carried out. The design of artificial intelligent character recognition machine. Its ability to recognize complex background images has a high success rate, which has been proved by experiments, and its adaptive ability is very strong.

Digital Background Calibration With Histogram of Decision Points in Pipelined ADCs

This brief presents a digital background calibration technique for pipelined analog-to-digital converters (ADCs). It is a histogram-based technique and called the correction with histogram of decision points (CHDP). In this method, the capacitor mismatch and residue amplifier gain error and nonlinearity are corrected by estimating the output code of decision points in the residue characteristic. In order to achieve adequate points, the threshold level of sub-ADC is changed and to increase the estimation accuracy, an algorithm named the mapping histogram is presented. CHDP does not require any special analog circuit and its digital logic is simple. Behavioral simulation results of a 12-bit 100 MS/s pipelined ADC indicate that the proposed calibration scheme improves signal-to-noise and distortion ratio and spurious free dynamic range from 34.1 and 35 dB to 68.2 and 75.8 dB, respectively, while needing about $1.5\,\, {\times } \,\, 10^{6}$ samples for the calibration of five stages.

A study on migration model in fish behavioral simulation

Fish behavioral models can be a beneficial tool for appropriate fisheries management and environmental impact assessment of ocean development. Especially, modelling of fish migration which is affected by the surrounding environment would be crucial. In the present study, we implemented several migration models in fish behavioral simulations. For a grid-based model which calculates spatiotemporal changes of population in each grid, we introduced a repulsive type migration model in which fish can sense the environment at only the grid where it stays. We also developed individual-based models which calculates the temporal change of coordinates for each individual fish, with migration models of repulsive and attracting type. The developed models are applied to fish behavioral simulations in Ise Bay, to investigate the characteristics of the models.