Binary Coded Decimal Research Articles

Design of a Novel Decimal to Multicode Converter in QCA Technology

Researchers are always looking for the improvement of existing methods. Today, CMOS technology is widely used, which has some advantages and disadvantages. One of the alternative methods for CMOS technology is QCA technology which compared to CMOS, has the advantages of low energy consumption and small occupied area. In this paper, by using the concepts and methods of QCA technology, a digital code converter is presented. In this converter, a new gate is used, which can produce outputs such as 4-input AND, 4-input OR, 4-input NAND, and 4-input NOR. The proposed converter has 10 inputs and 12 outputs. The 10 inputs are decimal numbers from 0 to 9, producing the output equivalent to excess-3, BCD, and gray codes. One of the advantages of this circuit is providing three different codes per input in just one circuit. In addition, due to the use of the new 4-input gate, the occupied area and the number of used cells were minimized. Simulations were performed by using QCADesigner-E version 2.2, and outcomes illustrated that the occupied area is equal to 0.29 μm2 and 380 QCA cells with 7 clock phases are used. The energy dissipation of the presented circuit is 171 meV. Also, given the favorable performance exhibited by the 4-input gate across various measurement parameters, it possesses the capability to be efficiently employed within larger and intricately designed circuits.

High-speed binary coded decimal digit multipliers with multiple error detection

Decimal arithmetic in the form of binary coded decimal (BCD) numbers is preferred in many financial, commercial and scientific applications. BCD multipliers are introduced as a key hardware unit to support both integer and floating-point decimal arithmetic operations. However, due to the increasing sensitivity of VLSI-based digital designs to the environmental effects, BCD multipliers are also prone to faults and errors similar to other arithmetic circuits. In addition, multiple error occurrence is possible in current digital systems especially in space applications which motivates to reach multiple error detection/correction in addition to single errors. In this paper, digit-by-digit BCD multipliers are introduced capable of multiple error detection with low delay overheads. To show the effectiveness of the proposed combined method, a 4-digit BCD multiplier is presented. Experimental results based on analysis and error injection-based simulations show that in addition to 100% single error detection, multiple errors can be detected with at least 99.6% probability in the 4-digit BCD multiplier as the implemented architecture.

Decimal to excess-3, BCD, and gray code converters with a novel 4-inputs block in QCA

Decimal to excess-3, BCD, and gray code converters with a novel 4-inputs block in QCA

Designs of BCD Adder Based on Excess-3 Code in Quantum-Dot Cellular Automata

Quantum-dot cellular automata (QCA) is a novel nano-electronic technology. QCA has attracted wide attention due to its extremely small feature sizes at the molecular or even atomic scale and ultra-low power consumption, making it a promising candidate to replace the complementary metal oxide semiconductor (CMOS) technology. Binary-Coded Decimal (BCD) adders are widely used in industrial computing. In this paper, we propose two types of excess-3 code (XS-3) based BCD adders (XS-3DAs). We use ripple-carry adders (RCA) and parallel binary adders (PBA) to construct XS-3DAs in QCA Designer tool, respectively. The PBA-based XS-3DA is constructed with a new correction logic. 4-bit, 8-bit, and 16-bit XS-3DAs are constructed based on the two proposed XS-3DAs, respectively. Comparisons show that, with the increase of design scaling, the delay and area-delay product (ADP) of the PBA-based XS-3DAs can be significantly reduced in comparison with that of the RCA-based XS-3DAs. Compared with the 16-digit RCA-based XS-3DA, the cell count, area, delay and ADP of the proposed 16-digit PBA-based XS-3DA are reduced by 37.88%, 25.99%, 37.68% and 53.88%, respectively.

Design of BCD Adder Using QCA Technology

Abstract: Quantum-dot Cellular Automata (QCA) technology is a promising alternative to traditional complementary metaloxide-semiconductor (CMOS) technology for implementing digital circuits due to its potential for high speed, low power consumption, and small size. In this paper, we present a design for a Binary Coded Decimal (BCD) adder using QCA technology. The BCD adder is a crucial building block for arithmetic operations in decimal representation. The proposed design uses QCA cells to perform the addition operation of two BCD digits, which are encoded as a 4-bit binary number. The design includes a full-adder circuit, a BCD-to-binary converter, and a carry-lookahead adder. Simulation results using QCA Designer software demonstrate the functionality and feasibility of the proposed BCD adder design. The proposed design provides a promising alternative to traditional CMOS-based BCD adders and can contribute to the development of QCA-based digital circuits

A power efficient fully adiabatic logic circuit design approach: application to inverter and 8421 to excess-3 code converter

Decreasing power consumption is the leading challenge for very-large-scale-integrated (VLSI) designers. This paper introduces an innovative prototype for a power-efficient standard or a fully-adiabatic binary-coded-decimal (BCD) 8421 to Excess-3 (XS-3) code converter. The proposed design is compared with traditional complementary metal oxide semiconductor (CMOS) as well as two popular fully adiabatic logic families: adiabatic dynamic CMOS logic (ADCL) and two phase clocked adiabatic static CMOS logic (2PASCL). This investigation was conducted at frequencies ranging from 100 to 900 MHz. The circuit employs 0.3 μm CMOS technology, with channel length and width set at 0.3 μm and 0.75 μm, respectively. The power savings for the proposed logic at 500 MHz when compared to standard CMOS logic, ADCL, and 2PASCL are 54.54%, 28.57%, and 16.67%, respectively.

Research on Real-Time Data Transmission and Feature Analysis Technology of Smart Tool Holder

Cutting force, vibration, and cutting temperature are the significant characteristics of the cutting process for real-time monitoring and optimization. Smart tool holder technology is one of the key technologies to effectively monitor the cutting process. In order to realize real-time monitoring of the cutting process, a data transmission and processing technology based on the smart tool holder is proposed. First, a data transmission scheme based on socket communication technology is developed. Then, a data transmission format based on Modbus protocol and BCD code is proposed. Finally, the feature analysis technology of real-time data is discussed for the requirements of real-time control and optimization of process parameters. The proposed technology is conducive to improving the data processing efficiency of the data transmission process of the smart tool holder and is of great significance to the standardization of data transmission based on the smart tool holder.

Modeling of Excess‐3 to BCD code converter for nano system using quantum‐dot cellular automata technology

AbstractThis work proposes a novel quantum‐dot cellular automata (QCA) layout for an Excess‐3 to BCD code converter for nano systems that is low in cell complexity. The suggested design uses a QCA clock‐phase‐based technique to evaluate integration with other complex circuits. The results obtained using the QCADesigner simulation tool demonstrate the superiority of the recommended layout over prior identical reverse counterpart designs by evaluating the cell numbers used, the space occupied, and the latency as design metrics. The suggested layout has a 56% decrease in occupied space and a 37.5% reduction in delay when compared to similar reverse counterpart scalable designs. In addition, the energy dissipation of the suggested structure was calculated and compared to previous comparable work (reverse equivalent) to confirm its reliability. The suggested circuit may be employed in bigger and more complicated circuits due to its advantage in numerous performance measurement parameters.

Design of efficient binary-coded decimal adder in QCA technology with a regular clocking scheme

Quantum-dot cellular automata (QCA) is a promising nanotechnology that offers an alternative to complementary metal-oxide-semiconductor (CMOS) technology. Nanoscale size, ultra-low power dissipation, and Terahertz range operating frequency make QCA more attractive to circuit designers. Recently, numerous designs of QCA have been proposed but aren't practically implementable due to random clocks in the design. In QCA designs, there is a need for proper clocking scheme to favour placement and routing and to facilitate QCA nano-computing synthesis. In this paper, a novel design of Binary-Coded Decimal (BCD) adder, based on QCA technology, with a realistic clocking scheme is presented. System simulations of the proposed designs are performed using QCA designer software Ver. 2.0.3 while power dissipation is investigated using the QCA Pro tool. Besides, in terms of power dissipation, the suggested QCA BCD adder dissipates 2.788 × 10−5 mW, whereas CMOS- based design consume 1.34 mW of power.

AMPS: An Automated Mesochronous Pipeline Scheduler and Design Space Explorer for High Performance Digital Circuits

In the Mesochronous Pipeline (MP), the clock period is the maximal of differences between the maximum/minimum delays of all stages. This value is less than the maximum delay between the memory elements, so MP is operating faster than the conventional pipeline (CP). To take full advantages of MP, in this paper, Automated Mesochronous Pipeline Scheduler (AMPS) for high performance digital circuits, is proposed which provides all allowed partitioning options generated by register allocation procedures obtained with varying maximum delay differences of stages. This allows a designer to select from design space produced by AMPS based on the desired specification. Unlike the traditional MP, AMPS utilizes automated scripts to extract the timing characteristics of the synchronizers and gates. This enables a designer to explore trade-offs between latency, power, and frequency. To evaluate our toolset, an 8-bit Carry Increment Adder (CIA), a 4-bit Binary-Coded Decimal (BCD) adder, a 4-bit ALU, and a set of circuits from ISCAS85 and ISCAS89 benchmarks are considered. All circuit level simulations are performed in the 65nm CMOS standard technology node. AMPS improves the frequency for its best solutions about 127.94% (on average) in comparison to the conventional pipeline scheme.

Impact of Radix-10 Redundant Digit Set [−6, 9] on Basic Decimal Arithmetic Operations

Redundant-digit decimal computer arithmetic, with the principal property of carry-free addition, has been the subject of several studies, as the relevant literature contains a wide variety of decimal digit sets and their binary representations. For example, symmetric decimal signed digit sets [-α, α], for α ∈ {5,6,7,8,9 }, and the asymmetric ones, such as [-8,9], [ -9,7], and [ 0,15 ], have been the basis of variant hardware architectures for decimal arithmetic operations. However, digit sets with the minimal 4-bit representations show better figures of merit. In this work, we present a new decimal digit set [-6,9], called diminished-6 overloaded decimal digit set (DODDS). Its special 4-bit representation contains two posibits (weighted 2³ and 2⁰) and two negabits (weighted 2² and 2¹). Design and implementation of the corresponding carry-free decimal adders and subtractors are thoroughly discussed. Furthermore, to cover the requirements of all possible DODDS applications in decimal multipliers, dividers, and square rooters, we provide adder/subtractor designs for a variety of input combinations of DODDS and binary coded decimal (BCD) operands, all with DODDS output (e.g., DODDS + BCD = DODDS, which is useful in BCD partial product reduction). Analytical and synthesis-based evaluations and comparisons with similar previous works show the notable merits of DODDS over the other redundant decimal digit sets.

A novel value-based multiplier architecture to multiply BCD numbers by powers of 10

A novel value-based multiplier architecture to multiply BCD numbers by powers of 10

A novel value-based multiplier architecture to multiply BCD numbers by powers of 10

A novel value-based multiplier architecture to multiply BCD numbers by powers of 10

Minimizing Ancilla Inputs and Garbage Outputs of Reversible BCD Multiplier

Over the last decades, designing reversible arithmetic circuits is one of the interesting research areas because of its ability to reduce power consumption in the circuits. This paper proposes two new design approaches of reversible binary-coded decimal (BCD) multiplier. The realization of such BCD multiplier has been achieved through binary multipliers, multiplexers, and a binary-to-BCD converter. Four types of multiplications, viz. [Formula: see text], [Formula: see text], [Formula: see text], and [Formula: see text] multiplications, have been utilized for such binary multiplication and are implemented parallelly as a combined multiplier to reduce ancilla inputs (AIs) and garbage outputs (GOs). We also propose a novel reversible BCD adder for a reversible binary-to-BCD converter with reducing AIs and GOs. The first design of the reversible BCD multiplier is integrated with the proposed BCD adder in the binary-to-BCD converter. Furthermore, the proposed reversible BCD adder is modified to reduce the AIs and the GOs, which is then integrated into the second design of the reversible BCD multiplier. The results offer appreciable reductions of AIs and GOs by at least [Formula: see text]16% and [Formula: see text]43%, respectively, compared to the existing designs found in the literature.

Implementation of Quantum-Dot Cellular Automata Based Efficient N-Bit BCD Adders Using Verilog

Quantum Dot Handheld Automatics is one of the best technologies in recent days for introducing a high speed and ultra-low powered digital circuit. Few binary and decimal arithmetic circuits were designed using an efficacious QCA-based algorithm. However, there is a substantial enhancement required yet if there is inbuilt availability of logic gates inside the QCA. Therefore, this article introduced innovative binary coded decimal (BCD) adders using QCA methodology. Simulation analysis discloses that proposed BCD adders obtained higher computational speed with lower delays and lesser area than conventional CMOS approaches.

On The Implementation of Densely Packed Decimal Number System Based Adder: Prospects and Challenges

Decimal digit number computation, through bit compression methodology, offers space and time saving, which can be incurred by the Chen-Ho and Densely Packed Decimal (DPD) coding techniques. Such coding techniques have a property of bit compression, like, three decimal digits can be represented by 10 bits instead of 12 bits in binary coded decimal (BCD) format. The compression has been obtained through the elimination of the redundant 0’s from BCD representation. This manuscript reports the pros and cons of the techniques mentioned above. The logic level functionalities have been examined through MATLAB, whereas circuit simulation has been erified through Cadence Spectre. Performance parameters (such as delay, power consumption) have been evaluated through CMOS gpdk45 nm technology. Furthermore, the best design has been chosen from them, and the decimal adder design technique has been incorporated in this paper.

An Efficient and Optimized Converter for Fast Binary to Decimal Conversion

ABSTRACT Decimal converter plays an essential role in decimal arithmetic operations. A decimal converter is used to convert binary partial products to Binary Coded Decimal. Here, the use of the converter cell decreases the delay of operation. In contrast to the previous shift + add3 implementations, the proposed cell is much more efficiently optimised due to which the speed of the overall conversion process is increased. The proposed cell shows an improvement in the delay of 9.33 and a power-delay product of 11.96 when compared to the previously proposed work. So, the proposed work can be a better substitute where faster conversions are required.

High-speed radix-10 multiplication using partial shifter adder tree-based convertor

A radix-10 multiplication is the foremost frequent operations employed by several monetary business and user-oriented applications, decimal multiplier using in state of art digital systems are significantly good but can be upgraded with time delay and area optimization. This work is proposed a more area and time delay optimized new design of overloaded decimal digit set (ODDS) architecture-based radix-10 multiplier for signed numbers. Binary coded decimal (BCD) to binary followed by binary multiplication and finally binary to BCD conversion are 3 major modules employed in radix-10 multiplication. This paperwork presents a replacement technique for binary coded decimal (BCD) to binary and vice-versa convertors in radix-10 multiplication. A novel addition tree structure called as partial shifter adder (PSA) tree-based approach has been developed for BCD to binary conversion, and it is used to add partially generated products. To meet our major concern i.e. speed, we need particular high-speed multiplication, hence the proposed PSA based radix-10 multiplier is using vertical cross binary multiplication and concurrent shifter-based addition method. The design has been tested on 45nm technology-based Zynq-7 field programmable gate array (FPGA) devices with a 6-input lookup table (LUTs). A combinational implementation maps quite well into the slice structure of the Xilinx Zynq-7 families field programmable gate array. The synthesis results for a Zynq-7 device indicate that our design outperforms in terms of the area and time delay.

Design and implementation of modified BCD digit multiplier for digit-by-digit decimal multiplier

Decimal multiplication is the most common operation in arithmetic applications. This paper presents an area-efficient digit-by-digit decimal multiplier using a modified binary-coded decimal digit multiplier. In general, a Binary-Coded Decimal (BCD) digit multiplier consists of two kinds of block, namely binary multiplier, and Partial Product Binary-to-Decimal (PPBD) converter. In the BCD digit multiplier design, the binary multiplier produces the partial product output by multiplying the multiplier value along with multiplicand, and the PPBD converter used to convert the binary partial product into the decimal value. Instead of the binary multiplier, this paper proposes a constant multiplier design to generate binary partial product values. Here, the multiplier value considers as the constant value. Further, the proposed architectures design and implement using both Field-Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC). When compared with the existing methods, the implementation results show that the proposed design effectively reduces the area requirement and delay.

Design and performance analysis of SOA-MZI-based Tbps all-optical gray converters with M-ary DPSK coded binary, gray, and octal inputs

We propose three different types of all-optical code converters with high data rates of 1 Tbps based on a semiconductor optical amplifier in Mach–Zehnder interferometer configuration. The gray code is a cyclic code, which is more suitable for accurate representation of numbers, error detection, correction, and rounding of decimal quantities. The OR and XOR logic gates are the key structures in the proposed design to convert binary inputs to gray (BITG), binary coded decimal (BCD) inputs to gray (BCDTG) and octal inputs to binary (OCTB) outputs. The output of proposed all-optical gray code converters is verified for all three types of input representations. The bit error rate is negligible for all the input combinations. The obtained average extinction ratio for all-optical code converters are 87, 84, and 78 dB. The optimum value of quality factor up to 59 is achieved at 0.1 A, ±5, and 0.3, respectively, for the injection current, linewidth enhancement factor, and optical confinement factor. For the first time to the authors’ knowledge, all-optical gray code converters yield high data rates of 1 Tbps for the semiconductor optical amplifier-Mach–Zehnder interferometer configurations using the M-ary differential phase-shift keying modulation scheme.