BCD Adder Research Articles

Optimizing Energy Efficiency in Digital Systems: An In-Depth Analysis of Power Gating in VLSI BCD Adders

Optimizing Energy Efficiency in Digital Systems: An In-Depth Analysis of Power Gating in VLSI BCD Adders

Design of High Speed BCD Adder Using CMOS Technology

Design of High Speed BCD Adder Using CMOS Technology

Survey Paper of BCD Adder with Different types of Adder

Survey Paper of BCD Adder with Different types of Adder

Enhancement in Speed of BCD Adder

Enhancement in Speed of BCD Adder

Reversible Gate Logic Adder with Parity Preserving Design

Reversible logic circuits have drawn attention from a variety of fields, including nanotechnology, optical computing, quantum computing, and low-power CMOS design. Low-power and high-speed adder cells (like the BCD adder) are used in binary operation-based electronics. The most fundamental digital circuit activity is binary addition. It serves as a foundation for all subsequent mathematical operations. The main challenge today is to reduce the power consumption of adder circuits while maintaining excellent performance over a wide range of circuit layouts. Error detection in digital systems is aided by parity preservation. This article proposes a concept for a fault-tolerant parity- preserving BCD adder. To reduce power consumption and circuit quantum cost, the proposed method makes use of reversible logic gates like IG, FRG, and F2G. Comparing the proposed circuit to the current counterpart, it has fewer constant inputs and garbage outputting devices and is faster.

BCD ADDER ENTERPRISE EXHAUSTING NOVEL REVERSIBLE LOGIC FOR STUMPY POWER APPLICATIONS

Reversible logic has garnered tremendous attention in the recent years owing to its capacity to lower the power dissipation which is the major criterion in low power digital design. It finds use in many fields, including nanotechnology, biotechnology, quantum computing, optical information processing, DNA computing, and advanced computing. This work introduces a novel reversible gate and uses it to create an improved reversible BCD adder. The suggested architecture is shown to be more efficient than current ones in terms of gate count, garbage output count, and quantum cost, according to a comparison result.

Design of BCD adder with five input majority gate for QCA

In the digital world BCD numbers play a pivotal role in constituting decimal numbers. New different technologies are emerging in order to obtain low area/power/delay factors to replace the CMOS technology. One such technology is quantum cellular automata (QCA) realization, through which many arithmetic circuits can be designed. This paper deals with the implementation of BCD adder with 5 input majority gates for QCA. The 3 input majority gate and an inverter are basic elements of QCA. In this project amalgamation of majority gates with 3 and 5 inputs are used instead of implementing the entire circuit using 3 input majority gate in the BCD i.e. mainly comprised by partly consumed gates and entirely consumed gates. The proposed is designed and functional verification is done by Verilog HDL and Modelsim version 10.4a. The proposed design has been verified and the delay of existing and proposed design is analysed using Xilinx tool. The numbers of partly consumed and entirely consumed gates are less when compared to the existing method of implementation. The delay is reduced compared to the existing system which shows the improvement of 9.84%. The drawback of crossovers that leads the difficulty in implementation and reduces the efficiency of the circuit is reduced in the proposed implementation.

Design and Implementation of Reduced Power Energy Efficient Binary Coded Decimal Adder

<p>This paper presents a novel architecture for low power energy binary represented decimal addition. The proposed BCD adder uses Binary to Excess Six Converter (BESC) block for constant correction to adjusts binary outputs exceeding 9 to correct decimal values and exploits the inherent advantage of reduced delay and switching, due to elimination of long carry propagation in second stage addition as in conventional design and switching OFF of the BESC block for decimal outputs less than 9. The proposed BESC-BCD adder has been designed using VHDL code and synthesized using Altera Quartus II. Experimental results demonstrates that the proposed decimal adder can lead to significant power savings and delay reduction compared to existing BCD adders which is realised in better power-delay product(PDP) performance. For example the PDP saving of the proposed BESC-BCD adder for a 1 digit and 2 digit addition implementations are 11.6% and 16.05% respectively, compared to the best of the designs used for comparison.</p>

New Majority Gate-Based Parallel BCD Adder Designs for Quantum-Dot Cellular Automata

In this brief, we first theoretically re-defined output decimal carry in terms of majority gates and proposed a carry lookahead structure for calculating all the intermediate output carries. We have used this method for designing the multi-digit decimal adders. Theoretically, our best ${n}$ -digit decimal adder design reduces the delay and area-delay product by 50% compared with previous designs. We have implemented our designs using QCADesigner tool. The proposed QCADesigner based 8-digit PBA-BCD adder achieves over 38% less delay compared with the best existing designs.

Efficient Realization of Vinculum Vedic BCD Multipliers for High Speed Applications

Decimal multipliers play an important role in our day to day life for commercial, financial and tax applications. Every processor multiplier acts as the basic building block which decides the performance of processor. Time and again research is going on to design high-performance, low-latency BCD multiplier architectures. This paper proposes a new approach to BCD multiplication using vinculum number system. The key feature of the proposed architecture uses entirely a new one digit ROM based BCD multiplier that uses vinculum numbers as operands. Using this one digit BCD multiplier, an N digit BCD multiplier is built by using the vedic vertical cross wire method (Urdhav Triyagbhyam). We have also used our proposed multi operand VBCD Adder (Vinculum BCD Adder) [my paper 26] to add the partial products. In this paper, we show that this approach is a promising alternative to conventional BCD multiplication or other decimal multiplication methods that use alternative decimal representations like 5211, 4221, Xs3 etc.

FPGA Logic Circuit Implementation and Synthesis with VHDL Programming: A Learning Approach

There are significant numbers of relevant research works available that concerns VHDL programming and Field Programmable Gate Array (FPGA) based hardware design, simulation and implementation. This is because; both the FPGA design and VHDL programming realization are quiet new and useful to accomplish various tasks in the field of research for digital system designed and development of miniaturized embedded system. It is found difficult to understand and put into practice by the learners in the tertiary institution, which still requires rapid training and development. In this paper, we design and demonstrate an FPGAlogic circuit using 4-bit BCD adders and parallel 4-bit comparator with a stepwise development of the vital soft logic design flow, simulation and timing analysis. It also presents an educational concept designed for complementing courses offered like FPGA prototype and ASIC design. This perception of FPGA-based design flow will facilitate learner’s understanding, skills and it will provide detailed insights into various aspects of microelectronics, digital logic systems design and VHDL programming. Keywords: Behavioral synthesis, BCD Adder, Four-bit comparator, FPGA prototype, Hardware design, Microelectronic, VHDL programming.

BCD Adder Design using New Reversible Logic for Low Power Applications

Objectives: Proposed a novel GDI (Gate Diffusion Input) based low power BCD adder to improve the performance further compared with existing BCD adder design using BBCDC reversible gates. Methods/Analysis: Reversible logic is one of the potential techniques observed for low power designs having lot of research scope in the fields of nanotechnology, which involves with quantum computing. One major advantage of reversible logic is its low power capability. The power dissipation, speed, circuit density are the main concerns of research today. The proposed GDI cell based BBCDC reversible logic is implemented using Microwind 2, with 120nm technology. Findings: The proposed GDI based BBCDC reversible adder is proved that there is 91.5% of reduction in delay, 80.7% of reduction in power dissipation, 64.58% of reduction in logic overhead, and 93.88% of reduction in area when compared with the CMOS logic. The design goal is to minimize PDP, in order to get low power with high-speed advantage. Novelty /Improvement: The proposed GDI based BCD adder using reversible logic results in 98.38% of PDP advantage over existing designs, hence more reliable with extended performance.

An Efficient Power Optimized 32 bit BCD Adder Using Multi-Channel Technique

Static power reduction is a challenge in deep submicron VLSI circuits. In this paper 28T full adder circuit, 14T full adder circuit and 32 bit power gated BCD adder using the full adders respectively were designed and their average power was compared. In existing work a conventional full adder is designed using 28T and the same is used to design 32 bit BCD adder. In the proposed architecture 14T transmission gate based power gated full adder is used for the design of 32 bit BCD adder. The leakage supremacy dissipated during standby mode in all deep submicron CMOS devices is reduced using efficient power gating and multi-channel technique. Simulation results were obtained using Tanner EDA and TSMC_180nm library file is used for the design of 28T full adder, 14T full adder and power gated BCD adder and a significant power reduction is achieved in the proposed architecture.

Design of Efficient BCD Adders in Quantum-Dot Cellular Automata

Among the emerging technologies recently proposed as alternatives to the classic CMOS, quantum-dot cellular automata (QCA) is one of the most promising solutions to design ultralow-power and very high speed digital circuits. Efficient QCA-based implementations have been demonstrated for several binary and decimal arithmetic circuits, but significant improvements are still possible if the logic gates inherently available within the QCA technology are smartly exploited. This brief proposes a new approach to design QCA-based BCD adders. Exploiting innovative logic formulations and purpose-designed QCA modules, computational speed significantly higher than existing counterparts is achieved without sacrificing either the occupied area or the cell count.

An enhanced high-speed multi-digit BCD adder using quantum-dot cellular automata

The advent of development of high-performance, low-power digital circuits is achieved by a suitable emerging nanodevice called quantum-dot cellular automata (QCA). Even though many efficient arithmetic circuits were designed using QCA, there is still a challenge to implement high-speed circuits in an optimized manner. Among these circuits, one of the essential structures is a parallel multi-digit decimal adder unit with significant speed which is very attractive for future environments. To achieve high speed, a new correction logic formulation method is proposed for single and multi-digit BCD adder. The proposed enhanced single-digit BCD adder (ESDBA) is 26% faster than the carry flow adder (CFA)-based BCD adder. The multi-digit operations are also performed using the proposed ESDBA, which is cascaded innovatively. The enhanced multi-digit BCD adder (EMDBA) performs two 4-digit and two 8-digit BCD addition 50% faster than the CFA-based BCD adder with the nominal overhead of the area. The EMDBA performs two 4-digit BCD addition 24% faster with 23% decrease in the area, similarly for 8-digit operation the EMDBA achieves 36% increase in speed with 21% less area compared to the existing carry look ahead (CLA)-based BCD adder design. The proposed multi-digit adder produces significantly less delay of (N –1) + 3.5 clock cycles compared to the N* One digit BCD adder delay required by the conventional BCD adder method. It is observed that as per our knowledge this is the first innovative proposal for multi-digit BCD addition using QCA.

Efficient Realization of BCD Multipliers Using FPGAs

In this paper, a novel BCD multiplier approach is proposed. The main highlight of the proposed architecture is the generation of the partial products and parallel binary operations based on 2-digit columns. 1 × 1-digit multipliers used for the partial product generation are implemented directly by 4-bit binary multipliers without any code conversion. The binary results of the 1 × 1-digit multiplications are organized according to their two-digit positions to generate the 2-digit column-based partial products. A binary-decimal compressor structure is developed and used for partial product reduction. These reduced partial products are added in optimized 6-LUT BCD adders. The parallel binary operations and the improved BCD addition result in improved performance and reduced resource usage. The proposed approach was implemented on Xilinx Virtex-5 and Virtex-6 FPGAs with emphasis on the critical path delay reduction. Pipelined BCD multipliers were implemented for 4 × 4, 8 × 8, and 16 × 16-digit multipliers. Our realizations achieve an increase in speed by up to 22% and a reduction of LUT count by up to 14% over previously reported results.

ENGLISH

Arithmetic and memory address computation are performed using adder operations. Hence, design of adders forms an important subset of electronic chip design functionality. BCD numbers play a prominent role in number system. To perform arithmetic operations on BCD numbers respective circuit has to be designed. To perform BCD addition, BCD adders are used. But the drawback with the BCD adder is low speed in operation due to delay in propagating carry output. This low speed operation will affect the operation of entire system in which it is used. As the technology is advancing day by day there is demand for chips with high speed. So to overcome this drawback, BCD adder using CLA is proposed in this paper. The proposed design is attempted here to reduce the delay and thereby increasing the speed of response. In existing BCD architecture, RCA is used to add numbers. The delay of RCA is high so it is effecting the speed of adder. So in the proposed design, CLA is used instead of RCA and also a parallel prefix network is to be used to produce the carry outputs for all stages. In this paper, a BCD adder using CLA is to be designed for 8, 16, 32, 64 and 128-bit size using VHDL with the help of ISE Xilinx design suite 14.1. The designed adder will be functionally verified by using ISIM simulator. Later, it will be synthesized using XST synthesizer to get the area (in terms of LUTS) and delay(ns). Finally, the designed BCD adders will be compared with conventional BCD adder in terms of delay(ns).

On Design of Parity Preserving Reversible Adder Circuits

In this paper novel parity preserving reversible logic blocks are presented and verified. Then, we present cost-effective parity preserving reversible implementations of Full Adder, 4:2 Compressor, Binary to BCD converter, and BCD adder using these blocks. The proposed parity preserving reversible BCD adder is designed by cascading the presented 4-digit parity preserving reversible Full Adder and a parity preserving reversible Binary to BCD Converter. In this design, instead of realizing the detection and correction unit, we design a Binary to BCD converter that its inputs are the output of parity preserving binary adder, and its output is a parity preserving BCD digit. In addition, several theorems on the numbers of garbage outputs, constant inputs, quantum cost and delay of the designs have been presented to show its optimality. In the presented circuits, the delay and the quantum cost are reduced by deriving designs based on the proposed parity preserving reversible blocks. The advantages of the proposed designs over the existing ones are quantitatively described and analysed. All the scales are in the Nano-metric area.

Optimized parity preserving quantum reversible full adder/subtractor

Reversible logic is one of the indispensable aspects of emerging technologies for reducing physical entropy gain, since reversible circuits do not lose information in the form of internal heat during computation. This paper aimed to initiate constructing parity preserving reversible circuits. A novel parity preserving reversible block, HB is presented. Then a new design of a cost-effective parity preserving reversible full adder/subtractor (PPFA/S) is proposed. Next, we suggested a new parity preserving binary to BCD converter. Finally, we proposed new realization of parity preserving reversible BCD adder. The proposed designs are cost-effective in terms of quantum cost and delay. All the scales are in the NANO-metric area.

Low power optimization of full adder, 4-bit BCD adder

Micro-electronic devices are playing a very prominent role in electronic equipments which are used in daily life. For electronic equipment battery life is important. So, in order to reduce the power consumption we implement a Sleepy technique to the electronic circuits. Sleepy technique is also called as power gating technique. In the power gating structure, a circuit operates in two different modes. In the sleep mode, the sleep transistors are turned OFF to reduce the leakage power. In the active mode, the sleep transistors are turned ON and can be treated as the functional redundant resistances, as circuit is in operation mode the power leakage should not be more than the basic full adder. When a sleepy transistor is placed at VDD, it is called as the "Header switch" and while it is placed near the ground, it is called as "Footer switch". Now in our project we implement this technique to the Full-adder and then it is used in 4-Bit Adder and 4-bit BCD Adder using 90nm scale technology. Without losing the CMOS logic a new full adder is designed by reducing the number of transistors which also leads to the reduction of chip size. In almost all electronic equipment full adder is used. So this project has been done with the aim of reducing the power consumption in the full adder circuit and implementing it in 4-Bit Adder and 4-Bit BCD Adder.