Batcher Network Research Articles

Low-Cost Sorting Network Circuits Using Unary Processing

Sorting is a common task in a wide range of applications from signal and image processing to switching systems. For applications that require high performance, sorting is often performed in hardware with application-specified integrated circuits or field-programmable gate arrays. Hardware cost and power consumption are the dominant concerns. The usual approach is to wire up a network of compare-and-swap units in a configuration called the Batcher (or bitonic) network. Such networks can readily be pipelined. This paper proposes a novel area-efficient and power-efficient approach to sorting networks, based on “unary processing.” In unary processing, numbers are encoded uniformly by a sequence of one value (say 1) followed by a sequence of the other value (say 0) in a stream of 0’s and 1’s with the value defined by the fraction of 1’s in the stream. Synthesis results of complete sorting networks show up to 92% area and power saving compared to the conventional binary implementations. However, the latency increases. To mitigate the increased latency, this paper uses a novel time-encoding of data. The approach is validated with two implementations of an important application of sorting: median filtering. The result is a low cost, energy-efficient implementation of median filtering with only a slight accuracy loss, compared to conventional implementations.

Shared concentration output queuing switch for multiple priority classes

AbstractIn B‐ISDN, it is important to handle a variety of traffic having different loss probability requirements by using the same network. Since the shared concentration output queuing (SCOQ) switch has shared transmission networks, focus has been on its switch. In multimedia communications, the QoS (quality of service) is required and satisfied. Moreover, it is important to satisfy the requirement for cell loss probability. The switch has the advantage that the number of switching elements is small. However, it is not enough to correspond to priority classes. In this paper, we propose the SCOQ switch model for multiple priority classes, which is structured with a batcher network and independent banyan networks for each class and output buffers. We evaluate the cell loss probability and mean waiting time by computer simulations and analysis. The cell loss probability of the high‐priority class can be reduced since more high‐priority cells have priority to be transmitted to output buffers than low‐priority cells. As a result, we show that the proposed model is useful in satisfying different requirements of the cell loss probability for multiple priority classes. © 2001 Scripta Technica, Electron Comm Jpn Pt 1, 85(2): 41–50, 2002

Batcher Banyan network with cell copy preparation stages for multicast switching

This paper considers an ATM switching network in a self-routing system for line switching, and proposes a Batcher Banyan network with a cell copy preparation network. The idea of this switching network is to consider the upper layer line in a communication network with a hierarchical structure, and to note that the traffic of a multicast connection is much smaller than the traffic of a one-to-one connection. The hardware scale is greatly reduced by allowing a small amount of blocking. More precisely, the Batcher Banyan network is used as the basic structure, and a cell copy preparation network with a small amount of hardware and a simple cell transfer algorithm is connected before the Batcher Banyan network. The cells are copied in the cell copy preparation network and the Batcher network. Routing is executed in the Batcher network and the Banyan network. The amount of hardware is greatly reduced compared to the conventional configuration in which the structure is divided into the copying network and the routing network. © 2001 Scripta Technica, Electron Comm Jpn Pt 1, 84(9): 54–63, 2001

Performance analysis of knockout ATM switch with batcher network for multiple priority classes

AbstractRecently, there has been a need for a network architecture with a variety of traffic. In order to meet the requirements, a conventional knockout switch for two priority classes has been proposed and evaluated by numerical calculations. However, the switch is analyzed for multiple priority classes even though there are many kinds of traffic in the network. In this paper, a knockout packet switch with a batcher network for multiple classes is proposed in order to satisfy different requirements for loss probability of packets with multiple classes. The proposed model involves sorting packets according to the small identification number of a priority class by a batcher network. Hence, it is possible to handle packets with multiple classes. The proposed switch consists of N modules structured with filters, batcher network, and output buffers. As a result, we show that the proposed model is useful in satisfying different requirements for packet loss probability with multiple classes. © 2001 Scripta Technica, Electron Comm Jpn Pt 2, 84(7): 10–18, 2001

Batcher Banyan network with cell copy preparation stages for multicast switching

AbstractThis paper considers an ATM switching network in a self‐routing system for line switching, and proposes a Batcher Banyan network with a cell copy preparation network. The idea of this switching network is to consider the upper layer line in a communication network with a hierarchical structure, and to note that the traffic of a multicast connection is much smaller than the traffic of a one‐to‐one connection. The hardware scale is greatly reduced by allowing a small amount of blocking. More precisely, the Batcher Banyan network is used as the basic structure, and a cell copy preparation network with a small amount of hardware and a simple cell transfer algorithm is connected before the Batcher Banyan network. The cells are copied in the cell copy preparation network and the Batcher network. Routing is executed in the Batcher network and the Banyan network. The amount of hardware is greatly reduced compared to the conventional configuration in which the structure is divided into the copying network and the routing network. © 2001 Scripta Technica, Electron Comm Jpn Pt 1, 84(9): 54–63, 2001

Knockout packet switch with batcher network for two priority classes

Various types of ATM switches have been widely studied and developed in B-ISDN. However, the conventional knockout packet switch cannot handle the multiple priority classes. We consider two class packets of class 1 and class 2. Class 1 packets have priority for packet loss probability. A knockout packet switch with batcher network for two class packets is proposed in order to improve the packet loss probability of priority packets. The proposed switch consists of N modules structured with filters, a batcher network, and output buffers. We evaluate the packet loss probability of each class by computer simulations and numerical calculations. We obtain the total mean waiting time at output buffers by numerical calculations. In addition, we show the mean waiting time at output buffers by computer simulations. It is found that our proposed switch is able to satisfy the requirements of packet loss probability for the two classes under uniform traffic. © 2000 Scripta Technica, Electron Comm Jpn Pt 1, 83(12): 49–57, 2000

Periodic Merging Networks

We consider the problem of merging two sorted sequences on constant degree networks performing compare—exchange operations only. The classical solution to this problem is given by the networks based on Batcher's Odd—Even Merge and Bitonic Merge running in log(2n ) time. Due to the obvious log n lower bound for the runtime, this is time-optimal. We present a new family of merging networks working in a completely different way than the previously known algorithms. They have a novel property of being periodic: this means that for some (small) constant k , each processing unit of the network performs the same operations at steps t and t+k (as long as t+k does not exceed the runtime). The only operations executed are compare—exchange operations, just like in the case of Batcher's networks. The architecture of the networks is very simple and easy to lay out. We show that even for period 3 there is a network in our family merging two n -element sorted sequences in time O(log n ). Since each network of period 2 requires $\Theta(n)$ steps to merge such sequences, 3 is the smallest period for which we may achieve a fast runtime. In order to improve constants standing in front of log n we increment the period and tune the construction using additional techniques. We achieve the runtime 9 . . . log_3 n $\approx$ 5.7 . . . log n for a network of period 4, and 2.25 . . . ((k+3)/(k-1+log 3))log n $\approx$ 2.25 . . . log n for a network of period k+3 , for $k\geq 1$ . Due to the periodic design, our networks have small area complexity. For instance, if each processing unit requires O(1) area and a comparator uses a single wire of width O(1) connecting the processing elements, then our networks require $\Theta((n/\log n)^2)$ area. This compares well with Batcher's networks that require area $\Theta(n^2)$ .

A contention resolution algorithm for input‐buffered batcher‐banyan networks

AbstractA simple algorithm for resolving output contentions in an input‐buffered Batcher‐banyan network is described. The basic idea in this algorithm is to let the binary nodes of the Batcher network participate in the arbitration process. The proposed algorithm is completely distributed and parallel; thus it scales well to large size switches. Furthermore, our algorithm is fair and requires an overhead that is significantly less than that due to the well‐known three‐phase algorithm. Two variations of the algorithm are described.

The Batcher-banyan self-routing network: universality and simplification

It is shown that the Batcher-banyan network performs as a universal self-routing switch when inputs with unassigned destinations are present. This is demonstrated by first proving that banyan networks can realize permutations represented by bitonic sequences, and then noting that the sorted output of the Batcher network can be viewed as a bitonic sequence. Two methods are proposed for reducing the complexity of the Batcher-banyan network. In the first method, one stage of the banyan network is eliminated by assigning proper destination tags to the unassigned inputs. In the second, a self-routing switch based on the binary-radix sorting scheme is shown to be more economical for a small number of lines.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A Broadband Packet Switch for Integrated Transport

This paper gives a broadband (total throughput approaching 1 terabit/s) self-routing packet switch design for providing flexible multiple bit-rate broadband services for an end-to-end fiber network. The switch fabric for the slotted broadband packet switch delivers exactly one packet to each output port from one of the input ports which request packet delivery to that output port. The denied requests would try again during the next slot. We discover an effective scheme, implemented by CMOS VLSI with manageable complexity, for performing this function. First, each input port sends a request for a port destination through a Batcher Sorting network, which sorts the request destinations in ascending order so that we may easily purge all but one request for the same destination. The winning request acknowledges its originating port from the output of the Batcher network, with the acknowledgment routed through a Batcher-banyan selfrouting switch. The acknowledged input port then sends the full packet through the same Batcher-banyan switch without any conflict. Unacknowledged ports buffer the blocked packet for reentry in the next cycle. We also give several variations for significantly improved performance. We then study switch performance based on some rudimentary protocols for traffic control. For the basic scheme, we analyze the throughput-delay characteristics for random traffic, modeled by random output port requests and a binomial distribution of packet arrival. We demonstrate with a buffer size of around 20 packets, we can achieve a 50 percent loading with almost no buffer overflow. Maximum throughput of switch is 58 percent. Next, we investigate the performance of the switch in the presence of periodic broadband traffic. We then apply circuit switching techniques and packet priority for high bit-rate services in our packet switch environment. We improve the throughput per port to close to 100 percent by means of parallel switch fabric, while maintaining the periodic nature of the traffic.