Batcher-banyan Network Research Articles

The Half Cleaner Lemma: Constructing Efficient Interconnection Networks from Sorting Networks

In general, efficient non-blocking interconnection networks can be derived from sorting networks, and to this end, one may either follow the merge-based or the radix-based sorting paradigm. Both paradigms require special modifications to handle partial permutations. In this article, we present a general lemma about half cleaner modules that were introduced as building blocks in Batcher’s bitonic sorting network. This lemma is the key to prove the correctness of many known optimizations of interconnection networks. In particular, we first show how to use any ternary sorter and a half cleaner for implementing an efficient split module as required for radix-based sorting networks for partial permutations. Second, our lemma formally proves the correctness of another known optimization of the Batcher-Banyan network.

High throughput Tandem-Banyan network switch based on SFQ technology

A Tandem-Banyan network switch (TBNS) based on superconductor single-flux-quantum technologies is described. Its switching core consists of multiple Banyan networks and transmission checkers (TMCs) connected sequentially. Numerical simulation demonstrated that the maximum throughput of TBNS is much higher than that of the input-buffer-type Batcher-Banyan network switch, while the amount of hardware is comparable with that of a Batcher-Banyan network switch. The two-bit code extraction part of the address decoder of the TMC circuit was designed and implemented using the SFQ cell library developed for NEC Nb standard fabrication process. The correct logic operation was experimentally observed with a bias margin of around ±10%. This switch is suitable for managing the huge amount of data traffic that will be carried in future backbone networks.

Batcher Banyan network with cell copy preparation stages for multicast switching

This paper considers an ATM switching network in a self-routing system for line switching, and proposes a Batcher Banyan network with a cell copy preparation network. The idea of this switching network is to consider the upper layer line in a communication network with a hierarchical structure, and to note that the traffic of a multicast connection is much smaller than the traffic of a one-to-one connection. The hardware scale is greatly reduced by allowing a small amount of blocking. More precisely, the Batcher Banyan network is used as the basic structure, and a cell copy preparation network with a small amount of hardware and a simple cell transfer algorithm is connected before the Batcher Banyan network. The cells are copied in the cell copy preparation network and the Batcher network. Routing is executed in the Batcher network and the Banyan network. The amount of hardware is greatly reduced compared to the conventional configuration in which the structure is divided into the copying network and the routing network. © 2001 Scripta Technica, Electron Comm Jpn Pt 1, 84(9): 54–63, 2001

Batcher Banyan network with cell copy preparation stages for multicast switching

AbstractThis paper considers an ATM switching network in a self‐routing system for line switching, and proposes a Batcher Banyan network with a cell copy preparation network. The idea of this switching network is to consider the upper layer line in a communication network with a hierarchical structure, and to note that the traffic of a multicast connection is much smaller than the traffic of a one‐to‐one connection. The hardware scale is greatly reduced by allowing a small amount of blocking. More precisely, the Batcher Banyan network is used as the basic structure, and a cell copy preparation network with a small amount of hardware and a simple cell transfer algorithm is connected before the Batcher Banyan network. The cells are copied in the cell copy preparation network and the Batcher network. Routing is executed in the Batcher network and the Banyan network. The amount of hardware is greatly reduced compared to the conventional configuration in which the structure is divided into the copying network and the routing network. © 2001 Scripta Technica, Electron Comm Jpn Pt 1, 84(9): 54–63, 2001

Shared concentration output queueing with middle buffer at input of batcher‐banyan network

A shared concentration output queueing (SCOQ) switch with middle buffers at the input of a batcher-banyan network is proposed in order to decrease the packet loss probability due to overflow. The proposed model can avoid packet loss due to blocking in the batcher-banyan network and decrease packet loss probability due to overflow. It uses a middle buffer at the input of the batcher-banyan network in the switching module. The proposed switch consists of N/2 output ports of each switching module. The switching module consists of a filter, a batcher-banyan network, middle buffers and output buffers. Switching operation is evaluated with respect to packet loss probability and mean waiting time by numerical calculation and computer simulation. We show that our proposed switch is able to decrease packet loss probability under uniform traffic conditions. ©1998 Scripta Technica, Electron Comm Jpn Pt 1, 82(3): 1–10, 1999

Shared concentration output queueing with middle buffer at input of batcher-banyan network

Shared concentration output queueing with middle buffer at input of batcher-banyan network

20.8 Gb/s GaAs LSI self-routing switch for ATM switching systems

An 8/spl times/8 self-routing hardware switch providing 20.8 Gb/s throughput has been developed for asynchronous transfer mode (ATM) switching systems. The basic architecture of this switch is a Batcher-Banyan network. A new mechanism for data processing and distributing high-speed signals is proposed. This switching system consists of three LSIs using a 0.5-/spl mu/m gate GaAs MESFET technology. These LSIs are a switching network LSI for exchanging packet cells with eight cell channels, a negotiation network for screening of cells destined for the same output port, and a demultiplexer LSI for converting the cell streams from the switching network LSI to the eight streams per channel. These LSIs are mounted in a 520-pin multichip module package. The total number of logic gates is 13.3 k, and the power dissipation is 24 W. The switching system fully operates at a data rate of 2.6 Gb/s, and its throughput is 20.8 Gb/s.

A recursive concentrator structure with applications to self-routing switching networks

A technique for constructing an N-input concentrator from two (N/2)-input concentrators and a stage of 2/spl times/2 switching elements is described. Recursive decomposition of each of the (N/2)-input concentrators yields a log/sub 2/N-stage switching network similar in topology to the inverse omega network. The control algorithm for setting the switching elements is shown to be a simple logic function of the activity bits of the inputs. An iterative cell that combines the functions of the control logic and the 2/spl times/2 switching element can be used as a building block to realize the entire concentrator. Applications of the concentrator structure as an interconnection fabric in fast packet switching is explored. This leads to an efficient self-routing network, similar in topology to the transposed Batcher-banyan network. >

Design and analysis of a multilink access subsystem based on the Batcher-banyan network architecture

A multilink access subsystem based on the Batcher-banyan network architecture is proposed. With this subsystem, multiple physical output links connecting a pair of switching nodes can be shared in an effective way. The subsystem is also configurational so that there is no restriction on any particular partition of physical output links. This is accomplished by executing the proposed multilink access algorithm on a modified Batcher sorter. It is shown that the required hardware can be integrated into the Batcher sorter, and the multilink access algorithm can be integrated with the contention resolution three-phase algorithm. The overhead incurred due to the running of the multilink access algorithm is calculated and the asymptotic performance analyses of the resulting single queue multilink access switch are presented. Results show that the proposed architecture has higher capacity than the unilink access counterpart, has low delay, and has low packet loss probability with small buffer size. >

A multiservice high-performance packet switch for broad-band networks

An input queued packet switch for broadband networks that supports data link connections and whose capacity is not constrained by the capacity of a single packet channel is described. The switch bandwidth is allocated at two different times. At connection setup time, an output data link (a channel group) is selected on which some bandwidth is reserved for the new call. At transmission time, specific channels within the data link are optimally allocated, slot by slot, to the packets addressed to that link, solving the output channel contention at the same time. The interconnection network of the switching is basically a Batcher-banyan network including the additional networks required to handle channel groups and to allocate bandwidth fairly at transmission time. Packet sequence integrity can be guaranteed for jitter-sensitive services, as the emulation of a circuit connection. It is shown that the channel group capability of the switch greatly improves the performance of standard input queued packet switches, so that input queuing with suitable data link capacities and output queueing give comparable performances.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The Batcher-banyan self-routing network: universality and simplification

It is shown that the Batcher-banyan network performs as a universal self-routing switch when inputs with unassigned destinations are present. This is demonstrated by first proving that banyan networks can realize permutations represented by bitonic sequences, and then noting that the sorted output of the Batcher network can be viewed as a bitonic sequence. Two methods are proposed for reducing the complexity of the Batcher-banyan network. In the first method, one stage of the banyan network is eliminated by assigning proper destination tags to the unassigned inputs. In the second, a self-routing switch based on the binary-radix sorting scheme is shown to be more economical for a small number of lines.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>