Baseband Signal Processing Algorithms Research Articles

An Adaptable and Scalable Generator of Distributed Massive MIMO Baseband Processing Systems

This paper presents an algorithm-adaptable, scalable, and platform-portable generator for massive multiple-input multiple-output (MIMO) baseband processing systems. This generator is written in Chisel hardware construction language, and produces instances that implement distributed massive MIMO base station (BS) processing, including channel estimation and beamforming. The generator can be reused for different MIMO systems and hardware datapath designs by changing the parameters. The generator is paired with a Python-based system simulator, which incorporated together can emulate a system testing various baseband signal processing algorithms. The field programmable gate array (FPGA) emulation is performed with generated instances using various parameter values. To demonstrate the algorithmic adaptability, a Golay-sequence-based channel estimation method, a beamspace calibration method, and a channel denoising algorithm are evaluated across a range of channel models. The performance of the generator, necessity of the algorithmic adaptability, and ease of hardware generation are evaluated and discussed. The emulated register-transfer level (RTL) implementation with different system parameters shows that with beamspace methods, the demodulation error vector magnitude is improved by up to 29.8%.

Open-source MATLAB code for GPS vector tracking on a software-defined receiver

The research regarding global positioning system (GPS) vector tracking (VT), based on a software-defined receiver (SDR), has been increasing in recent years. The strengths of VT include its immunity to signal interference, its capability to mitigate multipath effects in urban areas, and its excellent performance in tracking signals under high-dynamic applications. We developed open-source MATLAB code for GPS VT SDR to enable researchers and scientists to investigate its pros and cons in various applications and under various environments. To achieve this goal, we developed an conventional tracking (CT) SDR as a baseline to compare with VT. The GPS positioning estimator of this equivalent CT is based on an extended Kalman filter (EKF), which has exactly the same state, system, and carrier measurement models and noise tuning method as VT. This baseline provides users with a tool to compare the performance of VT and CT on common ground. In addition, this MATLAB code is well organized and easy to use. Users can quickly implement and evaluate their own newly developed baseband signal processing algorithms related to VT. The implementation of this VT code is described in detail. Finally, static and kinematic experiments were conducted in an urban and open-sky area, respectively, to show the usage and performance of the developed open-source GPS VT SDR.

Advanced Baseband Processing Algorithms, Circuits, and Implementations for 5G Communication

The rapid emergence of 5G communications technology and standardization has seen an accelerated transfer of theoretical concepts to advanced development and implementation. Not only are 5G baseband signal processing algorithms becoming more important, but also the co-design and implementation of corresponding circuits, architectures, and platforms are becoming necessary due to rapid standardization of 5G communications. This timely overview paper introduces circuits and systems (CAS) for key enabling technologies for the new 5G era: massive MIMO, mmWave baseband systems, NOMA schemes, advanced channel coding, and so on. The state-of-the-art research progress in these areas is summarized for interested readers to initiate discussion on limitations of existing solutions and open research problems that are looking for innovative solutions, especially in the CAS area. We hope this paper can bridge the gap between the theoretical investigation and application implementation for 5G communications.

Implementation of LTE system on an SDR platform using CUDA and UHD

In this paper, we present an implementation of a long term evolution (LTE) system on a software defined radio (SDR) platform using a conventional personal computer that adopts a graphic processing unit (GPU) and a universal software radio peripheral2 (USRP2) with a URSP hardware driver (UHD) to implement an SDR software modem and a radio frequency transceiver, respectively. The central processing unit executes C++ control code that can access the USRP2 via the UHD. We have adopted the Ettus Research UHD due to its high degree of flexibility in the design of the transceiver chain. By taking advantage of this benefit, a simple cognitive radio engine has been implemented using libraries provided by the UHD. We have implemented the software modem on a GPU that is suitable for parallel computing due to its powerful arithmetic and logic units. A parallel programming method is proposed that exploits the single instruction multiple data architecture of the GPU. We focus on the implementation of the Turbo decoder due to its high computational requirements and difficulty in parallelizing the algorithm. The implemented system is analyzed primarily in terms of computation time using the compute unified device architecture profiler. From our experimental tests using the implemented system, we have measured the total processing time for a single frame of both transmit and receive LTE data. We find that it takes 5.00 and 8.58 ms for transmit and receive, respectively. This confirms that the implemented system is capable of real-time processing of all the baseband signal processing algorithms required for LTE systems.

Software Simulation Method for Digital if GNSS Signal

Data simulation is an important auxiliary method for baseband signal processing algorithm design of digital IF GNSS receiver. Especially when the high sensitivity and high dynamic receivers are developed, or multipath and cross correlation mitigation techniques are considered, exact and complete tests under all kinds of necessary scenes can be carried out with the IF signal data which is generated by software simulation method. With this method, the developing efficiency can be improved and the cost can be cut down. In this paper, precise model of the IF signal is given firstly through analyzing GNSS receivers RF processing flow. Then, considering the discrete characteristic of software processing, the IF signal simulation flow and block of the simulation software are designed. Finally, the specific design process is given through a design example. When the IF signal simulation software is used for testing baseband signal processing algorithms, GNSS receivers IF signal data under every necessary test scene can be generated just by parameter adjustment.

A 70-Mb/s 100.5-dBm Sensitivity 65-nm LP MIMO Chipset for WiMAX Portable Router

In this paper, we present a low-power high-performance WiMAX chipset fully compliant with IEEE 802.16e specification corrigendum 1, 2 for mobile broadband access and WiMAX Forum system profile Wave2. The chipset is comprised of a 632.7-mW/24.99-mm2 modem/router chip and a 364-mW/11.05- mm2 dual-band 2 × 2 MIMO RF transceiver chip, both developed in 65-nm CMOS process. The proposed chipset is capable of handling a maximum peak WiMAX downlink (DL) throughput of 70 Mbps. Moreover, the chipset can reach up to -100.5-dBm sensitivity in a 10-MHz AWGN channel, which outperforms WiMAX Forum mobile radio conformance test (MRCT) by 9.5 dB. Such high sensitivity is due to the proposed low-noise high-linearity RF transceiver chip, which has 2.5-dB RX noise figure (NF) and -37-dB TX error vector magnitude (EVM), and the applied high-performance baseband signal processing algorithms. Several low-power design techniques-from SW level, firmware/DSP level, to HW module level-have been implemented to enable portable applications. The modem/router chip is highly integrated and has rich features and various interfaces for applications such as router or VoIP phone. Furthermore, this is the only published WiMAX chipset which has been in mass production.

Energy Aware Signal Processing for Software Defined Radio Baseband Implementation

The fast pacing diversity and evolution of wireless communications require a wide variety of baseband implementations within a short time-to-market. Besides, the exponentially increased design complexity and design cost of deep sub-micron silicon highly desire the designs to be reused as much as possible. This yields an increasing demand for reconfigurable/ programmable baseband solutions. Implementing all baseband functionalities on programmable architectures, as foreseen in the tier-2 SDR, will become necessary in the future. However, the energy efficiency of SDR baseband platforms is a major concern. This brings a challenging gap that is continuously broadened by the exploding baseband complexity. We advocate a system level approach to bridge the gap. Specifically, we fully leverage the advantages (programmability) of SDR platforms to compensate its disadvantages (energy efficiency). Highly flexible and dynamic baseband signal processing algorithms are designed and implemented to exploit the abundant dynamics in the environment and the user requirement. Instead of always performing the best effort, the baseband can dynamically and autonomously adjust its work load to optimize the average energy consumption. In this paper, we will introduce such baseband signal processing techniques optimized for SDR implementations. The methodology and design steps will be presented together with 3 representative case studies in HSDPA, WiMAX and 3GPP LTE.

Wireless Communications Transmitter Performance Enhancement Using Advanced Signal Processing Algorithms Running in a Hybrid DSP/FPGA Platform

This paper deals with digital base band signal processing algorithms, which are seen as enabling technologies for software-enabled radios, that are intended for the correction of the analog front end. In particular, this paper focuses on the design, optimization and testability of predistortion functions suitable for the linearization of narrowband and wideband transmitters developed with a hybrid DSP/FPGA platform. To select the best algorithm for the identification of the predistortion function, singular value decomposition, recursive least squares (RLS), and QR-RLS algorithms are implemented on the same digital signal processor; and, the computation complexity, time, accuracy and the required resources are studied. The hardware implementation of the predistortion function is then carefully performed, in order to meet the real time execution requirements.

A Design of the Signal Processing Hardware Platform for Communication Systems

In this letter, an efficient hardware platform for the digital signal processing for OFDM communication systems is presented. The hardware platform consists of a single FPGA having 900K gates, two DSPs with maximum 8,000 MIPS at 1GHz clock, 2-channel ADC and DAC supporting maximum 125MHz sampling rate, and flexible data bus architecture, so that a wide variety of baseband signal processing algorithms for practical OFDM communication systems may be implemented and tested. The IEEE 802.16d software modem is also presented in order to verify the effectiveness and usefulness of the designed platform.