Backside Fault Isolation Research Articles

Chromatic and spherical aberration correction for silicon aplanatic solid immersion lens for fault isolation and photon emission microscopy of integrated circuits

Current state-of-the-art in backside fault isolation and logic analysis utilizes solid immersion lens (SIL) imaging in the central configuration. An attractive advancement is the development and integration of an aplanatic SIL, which allows significant improvement in resolution, signal acquisition and isolation capabilities, especially for the 22nm node and beyond. However, aplanatic SIL configurations introduce both chromatic and spherical aberrations. We have developed backing objective designs capable of correcting for chromatic aberrations allowing application in photon emission microscopy, as well as deformable mirror designs and experiments that eliminate spherical aberrations of aplanatic SILs to account for variations in substrate thickness and off-axis imaging.

Performance of Forming Substrate into Solid Immersion Lens (FOSSIL) for Backside Fault Isolation Techniques

Abstract Conventional backside imaging takes advantage of silicon’s transmission of light which, based on the Plank relation (Eg = hc/λ), occurs at wavelengths greater than 1 µm. Because of diffraction, the lateral spatial resolution of backside imaging techniques is limited to about half the wavelength of the light source used, which is far too coarse to isolate faults in a typical IC. In this article, the authors explain how they overcome this limitation by reprofiling the backside of the silicon, forming spherically shaped domes. The raised convex surfaces act as solid immersion lenses that are shown to improve spatial resolution by nearly an order of magnitude. The degree of improvement is evaluated using backside emission microscopy (EMS), optical beam induced current (OBIC) imaging, and laser voltage probing (LVP) and the results are presented in the article.

Looking to the Future of FA: The Product Analysis Forum

Abstract The Product Analysis Forum (PAF), sponsored by the Quality Council of SEMATECH, has been chartered to facilitate the ongoing development of tools and techniques for semiconductor characterization and failure analysis. Drawing on input from industry experts, universities, and national laboratories, the PAF has identified critical needs in three areas: software fault isolation, backside fault isolation, and deprocessing & inspection. This article discusses the current state of deprocessing and inspection technology and provides insights into how some of the future challenges will be addressed.