Backplane Connector Research Articles

Simultaneously enhancing mechanical properties and electrical conductivity of Cu-0.5%Cr alloy as 5G connector material

With the rapid development of the 5 G communication, materials such as the high-speed backplane connector and the integrated circuit lead frame require higher strength and electrical conductivity. Copper alloys have been widely concerned due to their excellent electrical conductivity, thermal conductivity and good strength. A new method of preparing the Cu-0.5%Cr alloy by equal channel angular pressing (ECAP), deep cryogenic treatment (DCT) and aging treatment (AT) was proposed. The electrical conductivity, mechanical properties and microstructure of the Cu-0.5%Cr alloy were investigated, and the precipitation kinetics was analyzed. The results show that ECAP deformation and DCT treatment make the grains elongate and refine along the deformation shear direction. After four ECAP passes and DCT (12 h), the lamellar grains with the thickness of 200–300 nm were obtained, and the dislocation density was evidently increased. After the subsequent AT treatment, the fine Cr phase disperses uniformly at the grain boundaries and within the grains, and distributes on the matrix and along the dislocation lines. Compared with the solid solution, the results showed that after four passes of ECAP + DCT (12 h) + AT (425 ℃ × 1 h), the microhardness increased from 60.5 HV to 210 HV, the electrical conductivity changed from 27.9 % IACS to 69 % IACS, the strength improved from 262 MPa to 587 MPa, the elongation to failure decreased from 44.2 % to 21.9 %. The electrical conductivity was enhanced due to the second phase charge analysis showed that the scattering effect on electrons is weakened. The improvement of strength could be attributed to grain refinement and increase of dislocation density. Based on the Avrami empirical equation of precipitation kinetics analysis, the electrical conductivity equation and the phase change kinetics equation were established, and the relationship between aging time and electrical conductivity was established.

NRZ, Duobinary, or PAM4?: Choosing Among High-Speed Electrical Interconnects

Over the last several decades, the increasing data traffic in telecom, datacom, and high-performance computing has led to multi-gigabytes-per-second data transmission speeds in multiservice switches (MSSs), such as core routers and cross-connect switches [1]. A particularly challenging problem in this regard is the transmission of high-speed electrical data through the backplane in MSSs due to the high attenuation of current backplane materials and the limited bandwidth of backplane connectors [2].

Simulation-based design and optimization and fatigue characteristics for high-speed backplane connector

In high-speed interconnect systems, high-speed backplane connectors are widely utilized. Its mechanical reliability is related to the stability of entire application systems directly. Insertion–extraction force and fatigue characteristics are important factors that affect the reliability of high-speed backplane connectors. To enhance the reliability of high-speed backplane connectors, in this study, a single CAD/CAE parametric model of the contacts is established. Not only the dynamic analysis of the insertion and extraction process but also the electro-thermal-structure coupling of the contacts are carried out using finite element analysis. By changing the insertion position of male terminal, the length of female terminal, and the thickness of male terminal, the insertion–extraction force can be optimized. According to the simulation of the insertion–extraction force and the electric-thermal-structure coupling results, both the mechanical life of this connector and the thermal-mechanical fatigue life under electrifying condition are evaluated. The results show that the mechanical life and thermal-mechanical fatigue life were 376 cycles and 286 cycles, respectively. The design solutions can provide the reference for the structural design, optimization, and fatigue life prediction of high-speed backplane connector.

Investigation of the improvement of signal integrity in electrical circuits with degraded contacts using differential transmission

High-speed backplane connectors are extensively used in digital baseband communication circuits. Connector degradation may lead to deterioration of the integrity of digital signals and is one of the major causes of low communication quality. In this study, an accelerated test was used to produce degraded connector samples. Based on the degradation characteristics of the connector electrical contact surface, the differential transmission method was applied to enhance signal integrity in such degraded electrical contact circuits. Referring to the Gigabit Ethernet standard, the differential signal waveforms and eye diagrams of high-speed channels with un-degraded and degraded connectors were studied. Improvement of the circuit reliability by differential transmission was demonstrated from the perspectives of both experimental investigations and analysis using probability calculations.

Multi-Objective Optimum Design of High-Speed Backplane Connector Using Particle Swarm Optimization

This paper outlines a new procedure for computer modeling and optimum design for the dynamic mechanical and electrical study of a high-speed backplane connector, which is a key electrical interconnection technology in large communications equipment, ultra-high performance servers, supercomputers, industrial computers, high-end storage devices, and so on. The optimum structure design of contact pairs is important for a backplane connector in meeting multiple challenges in terms of minimizing the maximum insertion force and the contact resistance. Current optimization schemes, such as the quadrature method, are relatively complex. Therefore, we designed the connector contact pairs for simultaneously obtaining the proper insertion force and the contact resistance through a multi-objective particle swarm optimization (MCDPSO) method with simpler settings and faster convergence speed. In this paper, the required insertion force was minimized during the entire process, and the minimum contact resistance was maintained after insertion. To this end, an MCDPSO algorithm was proposed for the connector design. A dynamic weight coefficient was developed to calculate the interval values of the reserved solutions for the selection of the operator, and an external archive update based on roulette wheel selection and gbest selection strategies was developed to increase the diversity of the solutions. A set of optimal structure solutions of the contact pairs was obtained for the subsequent design optimization. The feasibility and effectiveness of the proposed method were verified by comparing with the results from ANSYS finite element simulation.

Radiation Physics and Design Guidelines of High-Speed Connectors

High-speed connectors contribute to system-level electromagnetic interference (EMI). Radiation from antenna-mode current and transmission-line (TL)-mode current is briefly reviewed with a backplane connector and an optical cage connector. The radiation from the high-speed connector with TL-mode current is analyzed in detail. The possible radiation mechanisms are analyzed respectively through Green's function method, steepest descent method, and electromagnetic compatibility studio method of moment. Design guidelines of high-speed connectors for EMI mitigation are proposed based on the analysis of radiation physics.

Experimental evaluation of NRZ and duobinary up to 48 Gbit/s for electrical backplanes

Transmission beyond 40 Gbit/s across a commercial Megtron 6, 11.5-inch electrical backplane is explored, and a record error-free serial electrical duobinary transmission of up to 48 Gbit/s including backplane connectors is demonstrated. Compared with non-return-to-zero (NRZ), the equalised duobinary transmission over the backplane demonstrates improved performance due to its higher bandwidth efficiency, and opens possibilities to increase the serial speed of backplane channels. Bit error rates are presented at different data rates and over different backplane channel lengths.

960 Gb/s Optical Backplane Ecosystem Using Embedded Polymer Waveguides and Demonstration in a 12G SAS Storage Array

An optical backplane ecosystem is described and demonstrated that is capable of multi-Tb/s bandwidth and is based on embedded polymer waveguides, passive optical backplane connectors, and midboard optical transceivers with bandwidth up to 28 Gb/s per lane. These systems provide the highest bandwidth-density, lowest power consumption, while maintaining the signal integrity. Ecosystems built around this architecture will provide the bandwidth-density required for next generation fabric interconnect for storage, switching, and routing applications in future high capacity generations of Data Centers and HPC systems. To demonstrate the applicability of this technology, it was used to provide embedded optical connectivity within a functional data storage enclosure.

XTRONIC®: Enabler of Improved Performance with Reduced Precious Metal Usage in Microelectronics

XTRONIC®, a tailored nanocrystalline nickel alloy, has been qualified as a new metal barrier layer replacing pure nickel in many traditional hard and soft gold applications. XTRONIC is produced using a proprietary combination of electroplating chemistry and pulse-reverse applied current waveforms that enables dynamic control of the deposited material's composition and grain structure. The resulting deposits have been shown to provide superior performance in a variety of areas that are critical to microelectronics. These improved performance metrics include resistance to corrosive environments, wear durability, wire bonding, and temperature aging performance. The novel suites of properties possible provide enhanced performance for microelectronics, and can also enable equivalent or improved overall performance even with significant reductions of precious metal use in many applications. Proven areas of application include high-speed backplane connectors and multiple printed circuit board applications such as dual in-line memory module (DIMM) and flash memory card (FMC) applications. In the current paper we focus on properties for printed circuit board applications.

Very High Lead Count SMT Backplane Connector Rework Process: Recognizing the Challenges

The ever growing demand for improved bandwidth, signal speeds, and performance in enterprise servers continues to drive increased circuit density and complex board designs. Single ended mode signaling is one design approach to address these challenges. A tightly integrated design team must carefully control the interfaces and trade-off complexity of chip and package designs to maintain power budgets at target performances. This single ended design approach has necessitated the use of very large (5040 contacts) surface mount connectors. These connectors are assembled to thick, densely wired, high copper content printed circuit boards which press the limits of conventional assembly and rework processes and tooling. Classical automated hot gas rework techniques, even with the best controls and practices in place, may not be capable of providing consistent, reliable connector rework. Extensive tooling modifications may also prove to be inadequate. Given these complex issues, in conjunction with shortening product development cycles, it is critical to define and investigate multiple rework approaches concurrently, so the probability of finding a manufacturable solution is greatly increased. This paper will discuss 1) the thermo-mechanical challenges encountered when trying to perform rework of this high lead count connector, 2) the tooling and process modifications attempted with respect to classical hot gas rework, and 3) the implemented solution which was full connector rework using a local vapor phase process. The local vapor phase process offers many advantages as the industry prepares for the transition to lead free when the RoHS server exemption expires. These advantages will also be discussed.

Optical Backplane Connectors Using Three-Dimensional Waveguide Arrays

Novel compact optical backplane connectors with 2-D arranged inputs/outputs (I/Os) are demonstrated. To meet the requirement of higher integration in an optical backplane system, we applied 3-D waveguide arrays with multichannel optical I/Os. Using laser writing and a wafer-lamination process, a single-mode waveguide array with 24 I/Os and a multimode waveguide array with 16 I/Os were, respectively, fabricated. In the assembly of the backplane connector, waveguide arrays were actively aligned and combined with polymer submounts, and then, the submounts were fixed to the backplane-connector housing. To ensure efficient coupling to the optical fibers, commercially available multimedia (MD) connectors were applied to the interface of the backplane connector. Using MD connectors with multichannel I/Os, we successfully obtained 10-Gb/s/ch transmission performance.

4 Gbit/s receiver with adaptive blind DFE

A serial backplane receiver with adaptive blind decision feedback equalisation (DFE) is proposed, which can operate at up to 4 Gbit/s over 1.2 m distance, which includes discontinuities due to the packaging and backplane connectors. A reduced complexity DFE implementation is achieved by biasing high-speed comparators. DFE coefficient calculation is not performed on every consecutive received sample, which significantly reduces the design complexity and power consumption.

A 96-channel FPGA-based Time-to-Digital Converter (TDC) and fast trigger processor module with multi-hit capability and pipeline

We describe an field-programmable gate arrays based (FPGA), 96-channel, Time-to-Digital converter (TDC) and trigger logic board intended for use with the Central Outer Tracker (COT) [T. Affolder et al., Nucl. Instr. and Meth. A 526 (2004) 249] in the CDF Experiment [The CDF-II detector is described in the CDF Technical Design Report (TDR), FERMILAB-Pub-96/390-E. The TDC described here is intended as a further upgrade beyond that described in the TDR] at the Fermilab Tevatron. The COT system is digitized and read out by 315 TDC cards, each serving 96 wires of the chamber. The TDC is physically configured as a 9U VME card. The functionality is almost entirely programmed in firmware in two Altera Stratix FPGAs. The special capabilities of this device are the availability of 840 MHz LVDS inputs, multiple phase-locked clock modules, and abundant memory. The TDC system operates with an input resolution of 1.2 ns, a minimum input pulse width of 4.8 ns and a minimum separation of 4.8 ns between pulses. Each input can accept up to 7 hits per collision. The time-to-digital conversion is done by first sampling each of the 96 inputs in 1.2-ns bins and filling a circular memory; the memory addresses of logical transitions (edges) in the input data are then translated into the time of arrival and width of the COT pulses. Memory pipelines with a depth of 5.5 μ s allow deadtime-less operation in the first-level trigger; the data are multiple-buffered to diminish deadtime in the second-level trigger. The complete process of edge-detection and filling of buffers for readout takes 12 μ s . The TDC VME interface allows a 64-bit Chain Block Transfer of multiple boards in a crate with transfer-rates up to 47 Mbytes/s. The TDC module also produces prompt trigger data every Tevatron crossing via a deadtimeless fast logic path that can be easily reprogrammed. The trigger bits are clocked onto the P3 VME backplane connector with a 22-ns clock for transmission to the trigger. The full TDC design and multi-card test results are described. There is no measurable cross-talk between channels; linearity is limited by the least-count time bin. The physical simplicity ensures low-maintenance; the functionality being in firmware allows reprogramming for other applications.

Solder connections for high frequency applications between flexible and rigid printed circuit boards

This article examines the backplane connector technology for high frequency use and presents a novel concept for shielded enclosures without air vents. The experimental soldering of connections between a flexible printed circuit (flex, for short) and a FR4-board as part of a backplane connector is presented. A very high contact density is reached by soldering vias on the flex to pads on the FR4; this soldering was performed both with ordinary Sn/Pb solder material and as well with lead-free solder alloy. The solder joints were examined using a scanning electron microscope (SEM) and the electrical properties of the flex/solder joint structure were measured.

An adaptive pam-4 5-Gb/s backplane transceiver in 0.25-μm CMOS

This paper describes a backplane transceiver, which uses pulse amplitude modulated four-level (PAM-4) signaling and continuously adaptive transmit-based equalization to move 2.5-GBd/s symbols totalling 5 Gb/s across typical FR-4 backplanes for total distances of up to 50 inches through two sets of backplane connectors. The 17-mm/sup 2/ device is implemented in a 0.25-/spl mu/m CMOS process, operates off of 2.5- and 3.3-V supply voltages, and consumes 1 W.

A 96-channel, 500 ps resolution TDC board for the BaBar experiment at SLAC

A TDC board has been designed and built to complete the readout of the Instrumented Flux Return of the BABAR experiment at the Stanford Linear Accelerator Center. The board has 96 input channels and makes use of 3 general purpose TDC chips designed at CERN, with time resolution up to 500 ps and configurable via a Test Access Port (IEEE standard 1149). Data are stored before readout in a multievent buffer. Communication with BABAR DAQ system is realized through 3 serial lines on the backplane connector. All the logic, including internal registers and the interfaces with the BABAR protocol and the TAP controller, is implemented in two fast FPGAs. The board is designed to work at 59.5 MHz clock frequency.

プログラマブルバックプレーン接続技術

We developed a programmable backplane unit that can reconnect lines between each pin of backplane connector. This backplane can connect 32 signal lines per circuit board to each board. As a result of transmission characteristic analysis, this backplane can be applied to high-speed interconnection (up to 200 MHz) between every circuit boards in this unit.

OC-12c digital crossconnect switch

This paper describes the design of an OC-12c crossconnect switch developed for the VISTAnet research testbed and installed in GTE's Parkwood central office. The crossconnect switch has been designed as SONET-compliant line terminating equipment and provides switching for up to 16 OC-12c signals. The system consists of up to eight trunk interface cards with two bidirectional OC-12 ports, a synchronous switch card, and a control module with craft interface to provide service monitoring, provisioning, and maintenance functions. Several novel concepts, such as distributed power systems and integrated electro-optical backplane connectors, were incorporated in the design of the crossconnect. The system was implemented using a judicious mix of GaAs, ECL, and CMOS technology. Particular attention was given to equipping the crossconnect with extensive diagnostic capability to facilitate network performance monitoring. Graphic user interface technology provides an easy interface for either operator or maintenance personnel.

A fiber optic connector designed for military optical backplanes

A fiber optic connector designed to meet military stress requirements has been demonstrated. This reliable optical card-edge (ROC) connector is a multifiber backplane connector (four fibers, blind mate). The connector uses a unique expanded beam coupling design and micromachined silicon optical subassemblies to provide optimum coupling under high levels of shock and vibration. An additional feature of the ROC connector is its ability to self-seal or shield the optical fiber ends when unmated, protecting the fibers and internal mechanisms from environmental contamination and abusive handling. The design features of the ROC connector are discussed with respect to military stress requirements, and the prototype test results are presented. >

An interactive 24-channel event-logging system based on the AIM 65 single-board microcomputer

Measures of the spontaneous behaviour of animals commonly involve the repetitive counting of behavioural events over successive periods of time following some experimental treatment. An automated event-logging system has been designed for such applications. The system is based on an AIM 65 microcomputer with 4 Kbytes of random-access memory and facilities for manual event-logging through the keyboard, or automatic logging via a signal-conditioning buffer, connected to the backplane connector of the computer. The control program is written in 6500 machine code and stored in an onboard, read-only, memory chip. The software generates a simple interactive dialogue for the selection of operating options which include manual or automatic modes, configuration of active channels, duration and number of logging cycles, and the choice of printed or transmitted output. The microcomputer can also be instructed to pause and then to restart, to print out its current status, or to abort. The system has been used over a period of 18 months in numerous experiments in this laboratory, and has proved to be reliable, accurate and entirely suited to its application.