Back End Of Line Interconnects Research Articles

Improving the Electromigration Life of Advanced Interconnects through Graphene Capping

Since the discovery of graphene, 2D materials are establishing a rapidly growing and promising field, with great potential for diverse applications given their excellent conductivity and high transparency. In particular, graphene can isolate external chemical reactions when applied to back-end-of-line (BEOL) interconnect metals, thereby preventing the oxidation of the interconnect metals. In addition, it can improve the conductivity and breakdown current density of interconnects. However, the thermal budget remains an important problem in BEOL interconnects. We demonstrate an advanced graphene deposition method using an in-house plasma plasma-enhanced chemical vapor deposition system, which offers low thermal budget and high stability. We also optimize carbon precursors to improve the quality of graphene on Ru and Co thin films. We show the improvement of electrical conductivity, electromigration lifetime, and maximum breakdown current density after capping Ru and Co interconnects with graphene. The electromigration lifetimes of the Ru and Co interconnects increase by 4 and 4.5 times, respectively, and their maximum breakdown current density increases by 17.6 and 10.6%, respectively. The results show that capping with graphene has a high potential in BEOL applications.

(Invited) Electrochemistry: Adventures in Metallization

Microelectronics has benefited enormously from electrochemistry, particularly in metallization. Metallizing through-holes in multilevel printed circuit boards was a major, successful application of electroless Cu (1). Electroless Co-based magnetic films deposited on non-magnetic electroless nickel films on rigid aluminum disks propelled the magnetic storage industry for years.A decade or more ago, it looked as if electroless Co(W)(P) was the ideal candidate to replace PVD Ta-based liners for CMOS back-end-of-line (BEOL) builds (2). Its cost undid it, however, despite meeting selectivity, diffusion barrier and reliability requirements. Electrolytic Cu has been an outstanding success for CMOS BEOL interconnect metallization, mostly because of its submicron feature superfilling ability (3).Following such success, electrolytic and electroless deposition methods have never been far from microelectronics researchers’ interest. In this talk, I will describe examples of electrochemical metallization in chip level, power conversion and MEMS areas that I have worked on. MRAM Final Interconnect Level Capping We recently developed a maskless, electroless, high-P-content, Ni(P) capping process for the final Cu bitline wiring level in our STTM MRAM 200 mm wafer test vehicles. This replaced a two litho mask, final aluminum metal interconnect level, drastically shortening process time.This novel protective layer enables functional testing of MRAM device memory state retention in an air atmosphere at elevated temperatures (4). The Ni(P)-coated wafers show virtually unchanged device resistance and magnetoresistance (MR) for MRAM 4Kb arrays. Magnetic Inductor Fabrication Magnetic inductors are increasing in importance in the ongoing development of integrated, on-chip power conversion. The latter is critical for realizing the dream of granular, DC-DC power delivery using dedicated voltage regulators (VR). Traditionally, the large size of the inductor component has impeded efforts to fabricate the VR in one module.We explored potentially manufacturable processes for magnetic-core inductors with enhanced inductance using through-mask electrodeposited Ni45Fe55 (Fig. 1) (5) and electroless Co(W)(P) layers (6). Electroless Co(W)(P) yoke material performed best overall, showing excellent magnetic properties, good magnetic anisotropy and coercivity of less than 0.1 Oe (6). The resistivity of the Co(W)(P) material was about 90-100 µΩcm; a value of 100 µΩcm is desired to limit yoke eddy current loss at high frequencies.Device scaling has finally brought magnetic inductor fabrication within reach of BEOL CMOS fabs. Magnetic Minimotor Fabrication High-aspect-ratio optical or X-ray lithography (LIGA) and electrodeposition processes were used to fabricate variable-reluctance, nearly planar, integrated minimotors with 6-mm-diameter rotors on silicon wafers (7). The motors comprised six electrodeposited Ni81Fe19 (Permalloy) horseshoe-shaped cores that surrounded the rotor. We formed copper coils around each core. LIGA processing provided vertical wall profiles, which were important for the rotor and stator core pole tips (see stator pole tip, feature D, in Fig. 2).We fabricated the rotors separately and slipped them onto the shaft after releasing them from the substrate wafer. Shaft fabrication via electrodeposition occurred as part of the stator fabrication process.The LIGA fabricated minimotor (100 μm thick Permalloy core with 40 μm thick rotor) represented the successful integration of aligned X-ray exposures and planarizing dielectric into a MEMS fabrication process, producing a working, five-layer magnetic motor. I will show some minimotor operational data.[1]. See papers in IBM J. Res. Develop., 28(6) (1984), available online.[2]. See, e.g., Y. Shacham-Diamand et al., J. Electrochem. Soc., 148 (2001) C162.[3]. P. C. Andricacos et al., IBM J. Res. Develop., 42, 567 (1998).[4]. E. J. O'Sullivan et al., 2019 Meet. Abstr. MA2019-02 916; doi: 10.1149/MA2019-02/15/916.[5]. E. J. O'Sullivan et al., ECS Transactions 50(10):93-105, doi: 10.1149/05010.0093ecst.[6]. N. Wang et al., MMM-Intermag, paper HG-11, 2013.[7]. E. J. O'Sullivan et al., IBM J. of Res. Develop., 42, 681 (1998). Acknowledgements The authors gratefully acknowledge the efforts of the staff of the Microelectronics Research Laboratory (MRL) at the IBM T. J. Watson Research Center, where some of the fabrication work described in this talk was carried out. Figure 1

Scaled Back End of Line Interconnects at Cryogenic Temperatures

At scaled nodes, Back End of Line (BEOL) interconnect resistance increases super-linearly and creates performance and energy bottlenecks. While it is known that metal resistance deceases with temperature, understanding and quantifying the behavior of interconnects from a foundry process design kit (PDK) at low temperature is critical for designing circuits and systems operating at cryogenic temperatures including Quantum and Superconducting Computers and other High-Performance Systems. In this letter we use parametric path based ring oscillators along with reference ring oscillators and Metal-on-Metal Capacitors for 22nm Fully Depleted Silicon on Insulator to measure RC delays of BEOL elements from room temperature to 4.2K. The extracted resistance of the elements show reduction of up to 30% for M1/M2, 33% for M3-M6 and 19% for Via1. With simple assumptions for interconnect structure, we perform least-squares fit of Fuchs-Sondheimer-Mayadas-Shatzkes (FS-MS) models with line-Edge roughness incorporated in the model using the Namba Model. The empirically fitted parameters track well with literature. The fitted model is within 3.7% error of all experimental results.

(Invited) Materials and Process Technologies for Scaling BEOL Interconnects

Historically, complementary metal-oxide-semiconductor (CMOS) technology was driven by geometrical scaling of the front-end-of-line (FEOL) transistor but it has slowed down significantly in recent years. On the other hand, back-end-of-line (BEOL) interconnects are projected to continue scaling aggressively to meet power, performance and area targets in advanced nodes. In this paper, we will introduce and review BEOL interconnect options targeting sub-7nm metal pitch with an emphasis on materials and process technologies.

(Invited) Electroless Deposition Revisited

After some early successes with electroless Cu for printed circuit board wiring (1), and the use of electroless Co-based magnetic films over non-magnetic electroless nickel films on rigid Al disks in the magnetic storage industry, for several years, electroless deposition was never far from researchers’ interest in the field of microelectronics. This was in part due to the hope that it might replace some of the expensive vacuum metallization methods with less expensive and selective, or self-aligned, deposition methods. Electrolytic Cu deposition won out over electroless Cu deposition for CMOS BEOL (back-end-of-line) interconnect applications for a variety of reasons, including superior filling characteristics, conductivity, electromigration resistance, solution additives, relatively more stable solutions, absence of co-evolution of H2 gas, and higher deposition rates. A decade or more ago, it looked as if it electroless Co(W)(P) (2) was the ideal candidate to replace PVD Ta-based liners for CMOS BEOL builds, but despite meeting selectivity, diffusion barrier and reliability requirements, it was discarded, in part for cost reasons. In addition to the subtlety of its mechanisms and range of solution formulations, electroless deposition has much to offer in terms of niche applications, which explains why it is often turned to first by researchers seeking creative deposition methods in the still emerging field of nanofabrication. Examples pertinent to both “mainstream” and exploratory uses of electroless deposition will be discussed in this talk, including: capping layers to prevent interconnect Cu oxidation; diffusion barriers, and novel uses in nanofabrication. However, a brief discussion of the strong and weak points of electroless deposition in the context of use in nano/microfabrication will first be undertaken. While electroless deposition is capable of depositing only a limited number of metals and alloys compared to electrodeposition, materials with unique properties, such as Ni(P) (corrosion resistance) and Co(P) (magnetic properties), are readily obtained by electroless deposition. It is in principle easier to obtain coatings of uniform thickness and composition using the electroless process, since one does not have the current density uniformity problem of electrodeposition. Most electroless solutions operate in a mode approximating kinetic control. Strongly-adsorbing solution stabilizers, usually present in ppm-type concentrations, tend to decrease the deposition rate, though the classic, environmentally-unfriendly stabilizers like Pb2+ have been largely phased out. Rates will be lower for features smaller than the stabilizer diffusion layer thickness, while the edges of features, which experience higher stabilizer levels due to enhanced nonplanar diffusion, may experience reduced deposition rates, or may remain uncoated in extreme cases. To compound this problem, dissolved O2 gas effects the mixed potential of the surface being coated in the electroless solution since it is capable of being reduced; since the dissolved O2 is present in low concentration, similar nonplanar diffusion effects on coverage uniformity are observed. The presence of solution stabilizers and dissolved O2 may impart a practical lower limit to feature size that can be reproducibly fabricated using electroless deposition; solution agitation will play a major role in determining this practical feature size limit. We recently developed a maskless, electroless, high-P-content, Ni(P) process to protect the final Cu bitline wiring level in our STTM MRAM test vehicle to enable functional testing in an air atmosphere at elevated temperatures for evaluation of MRAM device memory state retention. The process was developed as a replacement for the final Al level, and had a drastically shorter process time. We demonstrated an electroless Ni(P) that selectively deposited on Cu bit lines with effective spacing approaching 200 nm without shorting, for coating thicknesses up to ca. 50 nm, with excellent bitline coverage (few pinholes). This was achieved through optimization of Cu surface cleanliness using a wet clean solution, followed by surface catalyzation using an acidic Pd solution, and finally immersion in the electroless Ni(P) solution for a fixed time. Testing (R & MR type) of Ni(P)-coated wafers, showed virtually unchanged resistance and MR for MRAM 4Kb arrays encompassing a large range of device critical dimensions (CDs). Figure 1 shows a topdown SEM image of a region of electroless Ni(P)-coated Cu bitlines. [1]. Please refer to papers in IBM J. Res. Develop., Vol. 28, Issue 6, year 1984, available online. [2]. See, e.g., Y. Shacham-Diamand, Y. Sverdlov and N. Petrov, J. Electrochem. Soc., 148(3) (2001) C162. Acknowledgements The authors gratefully acknowledge the efforts of the staff of the Microelectronics Research Laboratory (MRL) at the IBM T. J. Watson Research Center, where some of the fabrication work described in this talk was carried out. Figure 1

Comparison of various low dielectric constant materials

To reduce the intrinsic resistance-capacitance delay of back-end-of-line (BEOL) interconnects in integrated circuits, low-dielectric-constant (low-k) materials with a dielectric constant (k) <4.0 have been introduced to be used as an interconnecting insulator from 130 nm technological node. In this paper, the physical and electrical characteristics, as well as the reliability, of various commercial low-k dielectric films with k values from 2.50 to 3.60, deposited by plasma-enhanced chemical vapor deposition were investigated. In addition to fluorinated silicate glass and dense organosilicate glass (OSG) low-k dielectric films, two porous OSG (P-OSG) films deposited using different sacrificial organic porogen precursors (alpha-terpinene (ATRP) and cyclooctane (C8H16)) were compared. The P-OSG films provide a lower k value than other low-k dielectric films, however, their resistance to the integration process is relatively low, resulting in a large increase in the k value and degraded electrical performance and reliability. Accordingly, the pursuit of the highly porous low-k dielectric films with a further low k value for the advanced technology nodes remains arguable. If a highly porous low-k dielectric film must be adopted in BEOL interconnects, the use of a sacrificial porogen precursor must be carefully considered because it would affect the properties of the resulting P-OSG films. In this study, the P-OSG film for the ATRP precursor exhibited better mechanical, electrical, and reliability characteristics than that for the C8H16 precursor.

Controlled Fracture and Mode-Mixity Dependence of Nanoscale Interconnects

Mechanical failures of back-end-of-line (BEoL) interconnects represent a critical yield and reliability concern for integrating new materials such as ultralow-permittivity (ultralow-k) dielectrics in advanced integrated circuits and for introducing new packaging technologies. The actual failure mode of the interconnects could vary with the BEoL processes, packaging, and assembly technology, as well as reliability and in-field stressing conditions. In this paper, we present a fundamental study of the crack propagation behavior of BEoL interconnects and its dependence on the mode mixity imposed by the external boundary condition. The effective fracture resistance has been measured for representative structures from upper, middle, and lower level interconnects. Under certain conditions where the failure path is uniform, the intrinsic fracture properties of the interlayer dielectric material and vias can be determined separately that allows a direct assessment of process-induced impacts on the integrated materials and their geometrical scaling properties.

Non-Contact, Sub-Surface Detection of Alloy Segregation in Back-End of Line Copper Dual-Damascene Structures

Alloy seedlayers for copper back-end of line interconnects have become common at technology groundrules of 45 nm and below, due to reliability requirements. The key requirement of the minority alloy component (e.g., Al or manganese, also referred to as the “dopant”) is that it segregates to the copper (Cu)/dielectric cap layer interface in order to promote adhesion between the Cu in the line and the dielectric capping layer. The segregation beneath the dielectric cap has a complex dependence on many process parameters and needs to be monitored across the wafer. In this paper, we present a contactless, in-line, fast, and reliable Kelvin probe technique for the sub-surface detection of alloy segregation in Cu interconnects for sub-22 nm technologies.

Development of a Cu and W Compatible PERR Clean in BEOL Advanced Interconnect Patterning

In back-end of line (BEOL), the fluorinated polymer deposited on dielectric sidewalls during patterning [1,2] must be removed prior to the subsequent processing steps to achieve good adhesion and coverage of materials (metals) deposited in the etched features. Recent results clearly showed the presence of a highly fluorinated layer deposited on the trench sidewalls during the plasma etch using a fluorocarbon based plasma [3]. The challenges related to the wet cleaning of such structures is the efficient removal of post-etch residues (PERR) by showing high selectivity and compatibility towards a variety of new materials exposed to the wet clean chemistry [4]. This study focuses on the use of acidic (pH:0.5-3) and alkaline (pH:8-13.5) aqueous based chemistries that are compatible with W and Cu, respectively. A schematic overview of a BEOL interconnect structure used for the N10 node (22 nm ½ pitch) is shown in Figure 1. The low-k material and hardmask that are used in this work/stack structure are respectively an OSG type of low-k material with a target value of k=2.4 (~20% open porosity) and TiN. Compatibility tests of different alkaline and acidic chemistries have been performed and proven to be compatible with the OSG 2.4 low-k dielectric material. The alkaline chemistries were compatible with Cu, while the acidic chemistries were compatible with W metal. The etch rate behavior of TiN was also checked. Spectroscopic ellipsometry, capacitance measurements (to measure k-value) and sheet resistance measurements were performed for this study. The test vehicle used to check the cleaning efficiency is a 45 nm ½ pitch BEOL trench short loop structure (Figure 2). A layer of low-k dielectric (80 nm) was first deposited on a 300 mm Si wafer, followed by the deposition of a 30 nm oxide HM and TiN layer (~25 nm), and a BARC/193-nm photoresist layer. The TiN layer was first etched using a HBr/Cl2 plasma, followed by the Oxide HM and OSG etch using a C4F8/CF4-based plasma (TEL Tactras). All dies are fully covered with the same type of 45 nm trench structures. A large choice of techniques was selected to characterize the cleaning efficiency of this test vehicle.One of the techniques used to investigate the cleaning of the CFx residue and TiN removal efficiency, is X-ray photoelectron spectroscopy (XPS). From figure 3, it is clear that the alkaline mixture removes almost completely the TiN within 2 min and at the same time the fluorine-containing residues have almost disappeared. The acidic formulated mixture removed TiFx (684.5 eV) completely while the CFx (688.3 eV) residues were only partially removed. A comparison of these acidic and alkaline formulated mixtures with citric acid and a TMAH:H2O2 mixture respectively, results in various cleaning efficiency but none of the commodity chemistries achieved complete removal of CFx and TiFx. The result obtained on a real device structure of 22.5 nm ½ pitch confirms the good performance obtained on the 45 nm ½ pitch BEOL structure. The SEM images shown in Figure 4 give an evidence that both Cu (M1 level) and the porous dielectrics are fully compatible with the chemistry. Electrical results using this alkaline chemistry, show a very good yield for CD lines, MF structure, and via chains will also be presented and discussed. [1] Y. Furukawa et al., Microelectron. Eng., 70, 267 (2003). [2] Q. T. Le et al., J. Electrochem. Soc. 159, H208 (2012). [3] T. Mukherjee et al., ECS Solid-St. Lett. 2, N11-N14 (2013). [4] E.Kesters et al.,Solid State Phenomena, 219, 201 (2015). Figure 1

Prediction of interfacial adhesion strength of nanoscale Al/TiN films passed through patterned BEOL interconnects

The patterned layout arrangement of back-end of line (BEOL) is an important factor among reliability issues of advanced interconnects technology. BEOL determines the likelihood of interfacial fracture when adhesion between dielectric materials and conductive metals becomes poor, especially when ultra low-k dielectric is introduced into the process of semiconductor devices. Interfacial delamination of dissimilar thin films comprising multi-level interconnects increases under external loading or thermal cycling stress during device manufacturing. An Al/TiN coating underneath an ordinary pattern of BEOL interconnects is selected in this research to estimate adhesive energy by using interfacial fracture theory based on finite element analysis. By adopting the framework of four-point bending test, the proposed simulated approach was validated before comparison of the adhesion of Al/TiN stacked coatings with experimental data. Analysis indicate that increasing dielectric thickness between interfaces of Al/TiN films and Al metal line patterns from 100nm to 600nm induces fracture growth with crack lengths exceeding 3.5mm. In addition, the foregoing driving force of fracture could be achieved because of Young’s modulus of dielectrics, which are larger than 70GPa.

(Invited) GaN HEMT Fabrication in a 200mm Si Foundry Environment: The Time Has Come

Relative to the Si industry, it is well known that the yield and cost of high performance III-V semiconductor devices and circuits have long been limited by low wafer volumes, increased substrate handling, the widespread use of metal liftoff techniques, and the use of time consuming electron beam lithography for sub ½ µm gate lithography. The silicon industry, on the other hand, has the benefit of high wafer volumes, highly automated cassette to cassette foundries, subtractive processing techniques, advanced deep sub micron optical lithography, and the Moore’s law paradigm (driving both equipment development and technology node development). Additionally, at a given technology node, the diameter of Si wafers processed in Si foundries has grown to 200-300mm. This in turn reduces cost of yielded product even further.As a result, the Si foundry environment has long been an attractive potential path for III-V device processing. What has been problematic, however, is that the low product volume of traditional III-V applications (such as RF and mixed signal), limited 100-150mm substrate diameter, and contamination concerns (due to use of Au and As based III-V compounds) have combined to limit the adoption of III-V materials by Si foundries. Thankfully, the recent substantial investment in gallium nitride (GaN) device technology may change this dynamic.GaN is chemically stable over most of the temperature range used in CMOS processing and is not perceived as inherently detrimental to CMOS from a contamination control perspective. This potential process compatibility with CMOS, and recent demonstrations of 200mm GaN on Si epitaxy, may enable GaN device technology to be gracefully phased in to aging 200mm CMOS foundries (to offset the decline of 200mm CMOS nodes). As a result, these foundries could potentially remain commercially viable and even thrive as 200mm GaN on Si power switching and RF applications in commercial and defense grow.To explore this possibility Raytheon has established a 200mm GaN on Si HEMT process within a commercial CMOS Si Foundry environment utilizing high yield Si-like processing techniques and Cu back end of line (BEOL) processes at Novati in Austin Tx. Our approach combines Raytheon’s 14 years of industry leading GaN HEMT experience (materials through system insertion) for defense applications with IQE’s own substantial materials know how, and Novati’s 200 & 300 mm Si foundry capability and expertise. To that end, based on our previous work1,2,3,4, we have implemented a Au-free, subtractively processed device cross section. The first mask release supporting this process cross section was released at Novati, our partner Si foundry, in 2013. More specifically, the mask set supports a 0.25µm GaN MISHEMT Front-End-Of-Line (FEOL) core transistor process that is reminiscent of cross sections used by traditional III-V foundries. The three metal coplanar waveguide (CPW) Back-End-Of-Line (BEOL) of the process, on the other hand, leverages single and dual damascene Cu interconnect technology developed for Si CMOS. Our Cu BEOL interconnects, however, have been adapted to handle the high current densities of GaN HEMTs and are in the process of being integrated with MIM capacitors and resistors to realize high performance RF circuits on the mask set.With our collaborator IQE, we have already demonstrated the scaling of GaN epitaxy to 200 mm via MBE (Raytheon) and MOCVD (IQE). Additionally, as shown in figure 1, process development using the mask set is well underway, and in fact transistor functionality has been demonstrated on 200mm wafers processed entirely at Novati's Si Foundry.As development continues, GaN HEMT material growth and process development will be optimized so that the performance of the all-Si foundry fabricated devices and circuits will be comparable to those fabricated in traditional III-V foundries on Si.

Bonding Structure of Model Fluorocarbon Polymer Residue Determined by Functional Group Specific Chemical Derivatization

The incorporation of porous low-k (k = 2.0) interlayer dielectrics (ILD) in BEOL (back-end-of-line) interconnects to reduce RC time delays continues to pose major integration challenges. Typically, low dielectric constants are achieved by replacing Si‐O bonds with Si‐C bonds to create nanoscale porosity in the silicon oxide dielectric matrix. 1 Porosity induced lowering of mechanical strength in carbondoped silicon oxide (CDO) makes them more susceptible to damage caused by common patterning processes such as fluorocarbon-based reactive ion etching (RIE). 1 Characterization of the post-RIE etch fluorocarbon polymer residues is essential because incomplete removal can cause problems with subsequent layers such as poor adhesion and coverage, fluoride contamination and poor electrical contact. 2 Electron and optical spectroscopy, electron microscopy, scanning probe microscopy and other probing tools have been used to identify and characterize model post-etch residues deposited on blanket Si substratesorcheckerboardpatternedwafersoflargedimensions. 3‐7 However, an improved understanding of chemical bonding structure of these fluoropolymer coatings is needed to facilitate more efficient process integration between trench etch and post-etch clean for small patterned features. In this study, the chemical bonding structure of model fluorocarbon polymer (MFP) residues deposited on a patterned CDO trench nanostructurewasdeterminedusingFouriertransforminfrared(FTIR) spectroscopy, X-ray photoelectron spectroscopy (XPS) and scanning electron microscopy (SEM). The MFP residues (6‐28 nm) were deposited on 90 nm low-k dielectric lines using fabrication processes closely mimicking actual manufacturing conditions. Enabled by precise background cancellation, FTIR revealed detailed chemical bondingcompositionoftheMFPresidues.Functionalgroupspecificchemistry in conjunction with IR and XPS analyses showed that MFP residue consisted of amorphous fluorinated polymers with significant branching, C=C bonds and C=O functional groups. The chemical bonding composition of deposited fluorocarbon layers can be modified by altering the plasma chemistry which can potentially lead to a more clean-efficient plasma etching process.

The Effect of Material and Process Interactions on BEOL Integration

In agreement with the ITRS roadmap, there have been several publications supporting the reduction in critical dimensions and the introduction of new materials to semiconductor processing (1,2,3). This paper highlights the observations and solutions to some of the critical material and process interactions encountered during the integration of the back end of line interconnect.

The impact of scaling on metal thickness for advanced back end of line interconnects

In this paper, a universal model to predict the amount of allowable metal thinning for the control of copper chemical–mechanical polishing (CMP) is presented. In the model, all the non-planarity, like dishing and erosion, resulted from the copper CMP process, is assumed accumulative. This amount after a certain levels of wiring should never be greater than the thickness of a single wiring level. Otherwise the circuit connections will be failure, since the metal is not at the right position. Based on this criterion, an equation is derived and the percentage of allowable metal thinning to the metal thickness is defined as F MT. The calculated F MT for the 180, 130, 90, 65 and 45 nm generations are 15%, 10%, 9%, 8%, and 7%, respectively. For the 130 and 90 nm generations, these numbers are close to the guidance of 10% recommended in the 2003 International Technology Roadmap for Semiconductors (ITRS). However, for the 65 nm and the 45 nm generations, the calculated F MT factors are smaller than that in the roadmap, suggesting that tighter copper CMP process control is required in the future generations.

Comparative studies of physical and chemical properties of plasma-treated CVD low k SiOCH dielectrics

The 0.13 μm technology uses Cu/low k materials for back-end-of-line (BEOL) process. In this paper, we studied and compared impact of etching and photoresist stripping (PRS) plasma on the physical and chemical properties of two CVD low k SiOCH films, Coral™ and Black Diamond™. They were treated with etching (C 4F 8/N 2/Ar) and O 2 or forming gas PRS plasma. The etching plasma did not cause Si–CH 3/Si–O degradation when compared to the PRS treatments. Forming gas PRS caused substantial –CH 3 loss and surface C depletion for both SiOCH films, especially for films treated with harsh processing conditions. O 2 PRS on low k films performed better than forming gas in terms of Δ k/ k 0, C depletion and stability of Si–CH 3/Si–O based on the k value comparison, surface and FTIR analyses. Moreover, soft O 2 PRS effectively removed C built-up on film surface after etching. The surface roughness and PRS etching rates of both films were also studied and compared. We had therefore successfully developed the soft O 2 plasma chemistry as a suitable PRS recipe for integration of Cu/CVD low k BEOL interconnects.