Average Noise Current Spectral Density Research Articles

Complementary Metal-Oxide-Semiconductor Symmetric Current-Conveyor Transimpedance Amplifier

This paper presents a novel symmetric current-conveyor transimpedance amplifier (SCC-TIA) implemented in a 0.13-μm CMOS technology for the applications of LiDAR systems, where a modifiedcascode configuration is newly proposed for input current buffer to deliver the photo-currents to the following voltage-mode inverter TIA without signal loss. Measured results of the proposed SCC-TIA demonstrate 69-dBΩ transimpedance gain, 410-MHz bandwidth, 13-pA/sqrt (Hz) average noise current spectral density, and 20-mW power dissipation from a single 1.2-V supply. Chip core occupies the area of 280×130 μm².

A 40-GHz Mirrored-Cascode Differential Transimpedance Amplifier in 65-nm CMOS

This paper presents a fully differential transimpedance amplifier (TIA) realized in a standard 65-nm CMOS process, where a novel mirrored-cascode (MC) input configuration is proposed for differential signaling, i.e., an NMOS cascode amplifier with a resistive feedback for negative output and its MC amplifier via an ac-coupling capacitor for positive output. For bandwidth extension, the third-order asymmetric transformers were carefully employed. Measured results of the proposed MC differential (MCD) TIA demonstrate 54-dB $\Omega $ transimpedance gain, 40-GHz bandwidth for 50-fF photodiode capacitance, $19.8-\text{pA}/\sqrt {\mathrm {Hz}}$ average noise current spectral density, ±10-ps group delay variation, and 55.2-mW power consumption. Eye diagrams for 32 Gb/s 215 –1 pseudo random binary sequence (PRBS) were measured with the input currents of 100–1.5 mApp. The chip occupies the area of 0.6 mm2 including I/O pads.

A Linear-Mode LiDAR Sensor Using a Multi-Channel CMOS Transimpedance Amplifier Array

This paper presents a linear-mode optical sensor for the feasible applications of unmanned vehicle LiDAR systems, in which a pulsed-erbium fiber laser is exploited as a light source and a 16-channel transimpedance amplifier (TIA) array is utilized in an optical Rx module with low-cost InGaAs PIN photodiodes. In particular, a voltage-mode CMOS feedforward (VCF-TIA) is newly proposed to achieve twice higher transimpedance gain with lower noise and similar bandwidth characteristics than a conventional inverter TIA, thereby enabling longer detection. Test chips of the 16-channel VCF-TIA array realized in a standard 0.18- $\mu \text{m}$ CMOS process demonstrate 76.3-dB $\Omega $ transimpedance gain, 6.3-pA/sqrt(Hz) average noise current spectral density, less than −33-dB crosstalk between channels, and 29.8-mW power dissipation per channel from a single 1.8-V supply. Automatic gain control is also equipped to extend input dynamic range for near-range detection. Hence, the proposed linear-mode optical sensor clearly detects the reflected optical pulses from the target of 5% reflection rate within the range of 0.5–25 m.

무인차량용 단거리 라이다 시스템을 위한 멀티채널 트랜스임피던스 증폭기 어레이

본 논문에서는 0.18um CMOS(1P6M) 공정을 이용하여 무인차량용 단거리 라이다 시스템을 위한 멀티채널 트랜스임피던스 증폭기(TIA) 어레이 회로를 구현하였다. 트랜스임피던스 증폭기 어레이 구조는 전압모드 4 × 4 채널 Inverter TIA 어레이와 전류모드 4 × 4 채널 Common-Gate(CG) TIA 어레이 두 가지를 설계했으며, 전체적으로 4 × 8 의 32-채널을 갖도록 설계하였다. 먼저, Inverter TIA는 피드백 저항을 가진 Inverter 입력구조와 CML 출력버퍼단으로 구성되어 있으며, 저잡음 및 저전력 특성뿐 아니라, virtual ground를 갖도록 설계함으로써 DC 전류조절이 가능하여 이득과 출력 임피던스 컨트롤이 가능하도록 하였다. 또한, CG-TIA는 on-chip bandgap reference로부터 bias 전압을 이용하고, 소스팔로워 출력버퍼를 사용하여 고주파수 이득을 높였으며, 기본적인 구조 상 CG-TIA는 채널당 칩 면적이 Inverter TIA에 비해 1.26배 작게 설계되었다. 포스트 레이아웃 시뮬레이션 결과, 제안한 Inverter TIA 어레이는 각 채널당 57.5-dBΩ 트랜스임피던스 이득, 340-MHz 대역폭, 3.7-pA/sqrt(Hz) 평균 잡음전류 스펙트럼 밀도, 및 2.84-mW (16채널 45.4-mW) 전력소모를 가졌다. CG-TIA 어레이는 채널당 54.5-dBΩ 트랜스임피던스 이득, 360-MHz 대역폭, 9.17-pA/sqrt(Hz) 평균 잡음전류 스펙트럼 밀도, 4.24-mW (16채널 67.8-mW) 전력소모를 가졌다. 단, 펄스 시뮬레이션 결과, CG-TIA 어레이가 200-500-Mb/s 동작속도에서 훨씬 깨끗하게 구분 가능한 출력펄스를 보였다.

1.25-Gb/s Regulated Cascode CMOS Transimpedance Amplifier for Gigabit Ethernet Applications

A transimpedance amplifier (TIA) has been realized in a 0.6-/spl mu/m digital CMOS technology for Gigabit Ethernet applications. The amplifier exploits the regulated cascode (RGC) configuration as the input stage, thus achieving as large effective input transconductance as that of Si Bipolar or GaAs MESFET. The RGC input configuration isolates the input parasitic capacitance including photodiode capacitance from the bandwidth determination better than common-gate TIA. Test chips were electrically measured on a FR-4 PC board, demonstrating transimpedance gain of 58 dB/spl Omega/ and -3-dB bandwidth of 950 MHz for 0.5-pF photodiode capacitance. Even with 1-pF photodiode capacitance, the measured bandwidth exhibits only 90-MHz difference, confirming the mechanism of the RGC configuration. In addition, the noise measurements show average noise current spectral density of 6.3 pA//spl radic/(Hz) and sensitivity of -20-dBm for a bit-error rate of 10/sup -12/. The chip core dissipates 85 mW from a single 5-V supply.

A 65-mW 5-Gb/s/ch current-mode common-base transimpedance amplifier array for optical interconnects

A four-channel photoreceiver array with 20-Gb throughput has been realized in a 0.8-μm Si-SiGe heterojunction bipolar transistor technology for parallel optical interconnect applications. Each channel includes a transimpedance amplifier exploiting the current-mode common-base input configuration to achieve efficient isolation of the large input parasitic capacitance. The chip module demonstrates the -3-dB bandwidth of 4.1 GHz for 0.25-pF photodiode capacitance, the midband transimpedance gain of 3.2 k/spl Omega/, the average noise current spectral density of 7.4 pA//spl radic/(Hz), and -19-dBm optical sensitivity for the bit-error rate of 10/sup -10/. Also, the array obtains less than -20-dB crosstalk between adjacent channels. The chip dissipates 65 mW in total from /spl plusmn/2.5-V supply.