Auxiliary Logic Research Articles

Enhanced sensitive phase alpha plane scheme against high resistance ground faults

Abstract Phase-based Alpha (α) Plane Relaying (APR) scheme has numerous advantages over the Current Differential Relay (CDR) for transmission line protection. Since the large Restraining Region (RR) in the APR makes high security against CT saturation, channel delay, line charging current and synchronization error. However, the APR loses its sensitivity for high resistance ground faults, especially single line to ground faults under outfeed conditions. Also, losing its dependability under close-in low resistance three-phase faults. Thereby, the sequence-based APR provides enhanced sensitivity with the cost of computational burden and complexity. Hence, in this paper, the concept of the average value (I Avg) of both end instantaneous currents is used as an auxiliary logic. In which, the polarity of I Avg is incorporated as an add-on logic to the conventional APR to confirm high resistance internal faults. Thereby, the requirement of sequence components can be avoided (negative and zero). To validate the proposed auxiliary logic, it is tested for the WSCC (Western System Coordinating Council) 9-bus, 110 kV, 50 Hz. System. The simulated results under various fault cases found authenticated results. In addition, the comparative assessment and validation with real-world data reveal the enhanced sensitivity of the proposed logic under high-resistance ground faults.

Full-function logic circuit based on egg albumen resistive memory

The logic gate is the basic unit of a digital circuit structure. The operation, memory, I/O, and other reading and writing functions of computer systems require logic circuits. Logic gates based on resistive memory can make existing integrated circuits denser, smaller, faster, and use fewer devices. In this paper, Al/polymethyl methacrylate (PMMA)/egg albumen (EA):Au nanoparticles/PMMA/Al multilayer biological resistive random access memory was prepared based on the natural biological material—egg albumen (EA). The device has bipolar switching behavior, a higher switching current ratio, a lower threshold voltage, and better stability. A circuit based on auxiliary logic is constructed using this device, and the logic functions of AND, OR, NOT, NAND, and NOR are realized. This device provides an effective potential solution for implementing high-performance electronic devices and large-scale integrated circuits.

An auxiliary logic on trees: On the tower-hardness of logics featuring reachability and submodel reasoning

We describe a set of simple features that are sufficient in order to make the satisfiability problem of logics interpreted on trees Tower -hard. We exhibit these features through an Auxiliary Logic on Trees (ALT ), a modal logic that essentially deals with reachability of a fixed node inside a forest and features modalities from sabotage modal logic to reason on submodels. After showing that ALT admits a Tower -complete satisfiability problem, we prove that this logic is captured by four other logics that were independently found to be Tower -complete: two-variables separation logic, quantified computation tree logic, modal logic of heaps and modal separation logic. As a by-product of establishing these connections, we discover strict fragments of these logics that are still non-elementary.

Analysis of stepwise charging limits and its implementation for efficiency improvement in switched capacitor DC–DC converters

In this work we analysed the stepwise charging technique to find the limits from which it is beneficial in terms of load capacitance and charge–discharge frequency. We included in the analysis practical limitations such as the consumption of auxiliary logic needed to implement the technique and the minimum size of auxiliary switches imposed by the technology. We proposed an ultra-low-power logic block to push these limits and to obtain benefits from this technique in small capacitances. Finally, we proposed to use a stepwise driver in the driving of the gate capacitance of power switches in switched-capacitor (SC) DC–DC converters. We designed and manufactured, in a 130 nm process, a SC DC–DC converter and measured a 29% energy reduction in the gate-drive losses of the converter. This accounts for an improvement of 4% (from 69 to 73%) in the overall converter efficiency.

A Mode Selected Mixed Logic Dynamic Model and Model Predictive Control of Buck Converter

A Mixed Logic Dynamic (MLD) model and control method based on mode selection are proposed for the Buck convertor. In establishing the hybrid system model, the factors such as the inductor current are neglected, and the Model Predictive Control (MPC) is used to switch the most favorable working state of the control target. Since the modeling process ignores the inductance and current, it is necessary to convert the optimization prediction control resulting to avoid the problem that the model is inconsistent with the control object. The method proposed in this paper uses fewer auxiliary logic variables and mixed logic variables in the modeling process, simplifying the model and improving the solution speed. This method can not only make the Buck converter work in the Continuous Current Mode (CCM) but also work in the Discontinuous Current Mode (DCM), extending the adjustment range of the Buck converter. The simulation results show that the proposed method has a better control performance than the traditional MLD model.

How to Precisify Quantifiers

I here argue that Ted Sider's indeterminacy argument against vagueness in quantifiers fails. Sider claims that vagueness entails precisifications, but holds that precisifications of quantifiers cannot be coherently described: they will either deliver the wrong logical form to quantified sentences, or involve a presupposition that contradicts the claim that the quantifier is vague. Assuming (as does Sider) that the “connectedness” of objects can be precisely defined, I present a counter-example to Sider's contention, consisting of a partial, implicit definition of the existential quantifier that in effect sets a given degree of connectedness among the putative parts of an object as a condition upon there being something (in the sense in question) with those parts. I then argue that such an implicit definition, taken together with an “auxiliary logic” (e.g., introduction and elimination rules), proves to function as a precisification in just the same way as paradigmatic precisifications of, e.g., “red”. I also argue that with a quantifier that is stipulated as maximally tolerant as to what mereological sums there are, precisifications can be given in the form of truth-conditions of quantified sentences, rather than by implicit definition.

Variable precision arithmetic circuits for FPGA-based multimedia processors

This brief describes new efficient variable precision arithmetic circuits for field programmable gate array (FPGA)-based processors. The proposed circuits can adapt themselves to different data word lengths, avoiding time and power consuming reconfiguration. This is made possible thanks to the introduction of on purpose designed auxiliary logic, which enables the new circuits to operate in single instruction multiple data (SIMD) fashion and allows high parallelism levels to be guaranteed when operations on lower precisions are executed. The new SIMD structures have been designed to optimally exploit the resources of a widely used family of SRAM-based FPGAs, but their architectures can be easily adapted to any either SRAM-based or antifuse-based FPGA chips.