Automotive Real-time Systems Research Articles

MIAT Efficient analysis of adaptive variable-rate tasks

Response time analysis of adaptive variable-rate tasks (AVR tasks) is a challenging problem in automotive real-time systems. While in periodic event-triggered systems, the worst-case response time is easy to determine, the analysis of AVR tasks has to deal with an exponentially growing number of combinations of execution paths. Each execution path has a specific dynamic behavior. In this paper, we present a new approach for reducing the number of potential worst-case combinations by introducing an intuitive view on the relation of start and end speeds given by speed-phase diagram. Here we propose a minimal inter-arrival time algorithm (MIAT) which is built on time constant lines (isochrones) in a speed-phase diagram first introduced in this work. Compared with previous work, the MIAT algorithm is more accurate and shows a significant improvement in runtime.

Evaluation and modeling of the supercore parallelization pattern in automotive real-time systems

Abstract Today’s combustion engines are finely tuned to deliver as much performance as possible out of only little amount of fuel. To achieve such high efficiency a lot of computational power is needed in Engine Management Systems (EMSs), which nowadays is delivered by multicore processors. However, this is a challenge for software developers as most of them are not yet familiar with the specifics of multicore programming. The real-time requirements of an EMSs further complicates software development. This paper revisits the supercore embedded Parallel Design Pattern, which reduces the fork-join-overhead by ensuring concurrent execution of coupled tasks. To test our pattern we implemented two algorithms using the supercore pattern on a state of the art EMS with an Infineon Aurix TC39x processor. We show that by using the supercore pattern we were able to reduce the response time of the analyzed functions and to achieve a speedup of up to 1.97 on four cores. We also analyzed the effect of the non-uniform memory architecture, which required specific optimization measures and limits the achievable speedup to 2 on four cores. We also show how the supercore pattern is modeled by previously defined extensions to the Electronics Architecture and Software Technology - Architecture Description Language (EAST-ADL) and AUTomotive Open System ARchitecture Standard (AUTOSAR).

SimTrOS: A heterogenous abstraction level simulator for multicore synchronization in real-time systems

Abstract To provide a common ground for the comparison of real-time multicore synchronization protocols we developed a framework that supports heterogenous levels of abstraction for simulated functionality and simulated timing. Our intention is to make the simulator available to the real-time research community and industrial users. For the latter we initially focus on automotive real-time systems. This paper describes the simulation framework and the novel idea of heterogenous abstraction levels that lies at the heart of its design. Notwithstanding the clear focus, we believe that the simulator itself as well as the concept of heterogenous abstraction levels can be useful in a significantly broader way.

Architectural Exploration of Heterogeneous Multiprocessor Systems for JPEG

Multicore processors have been utilized in embedded systems and general computing applications for some time. However, these multicore chips execute multiple applications concurrently, with each core carrying out a particular task in the system. Such systems can be found in gaming, automotive real-time systems and video / image encoding devices. These system are commonly deployed to overcome deadline misses, which are primarily due to overloading of a single multitasking core. In this paper, we explore the use of multiple cores for a single application, as opposed to multiple applications executing in a parallel fashion. A single application is parallelized using two different methods: one, a master-slave model; and two, a sequential pipeline model. The systems were implemented using Tensilica's Xtensa LX processors with queues as the means of communications between two cores. In a master-slave model, we utilized a course grained approach whereby a main core distributes the workload to the remaining cores and reads the processed data before writing the results back to file. In the pipeline model, a lower granularity is used. The application is partitioned into multiple sequential blocks; each block representing a stage in a sequential pipeline. For both models we applied a number of differing configurations ranging from a single core to a nine-core system. We found that without any optimization for the seven core system, the sequential pipeline approach has a more efficient area usage, with an area increase to speedup ratio of 1.83 compared to the master-slave approach of 4.34. With selective optimization in the pipeline approach, we obtained speed ups of up to 4.6× while with an area increase of only 3.1× (area increase to speedup ratio of just 0.68).

BASEMENT: an architecture and methodology for distributed automotive real-time systems

BASEMENT/sup TM/ is a distributed real-time architecture developed for vehicle internal use in the automotive industry. BASEMENT covers application development, as well as the hardware and software that provide execution and communication support. This paper gives an overview of the BASEMENT concept, as well as presenting two system realizations. The first realization is based on the commercial real-time kernel Rubus, while the second is an ultra-dependable architecture (DACAPO) with provisions for fault tolerance at various system levels. BASEMENT is designed for the automotive systems of the future. These systems will be required to simultaneously handle multiple safety critical functions and a large number of less critical functions. All of these features are to be provided at a production cost substantially lower than that of current systems, and, at the same time, with a reliability allowing vehicles to be built without mechanical backup systems, even for safety critical subsystems such as braking and steering.