Automatic Test Pattern Generation Process Research Articles

Application of machine learning methods for automatic test pattern generation process optimization during circuit design

Application of machine learning methods for automatic test pattern generation process optimization during circuit design

Test Pattern Generation and Critical Path Selection in the Presence of Statistical Delays

The statistical delay of a path is traditionally modeled as a Gaussian random variable assuming that the path is always sensitized by a test pattern. Its sensitization in various circuit instances varies among its test patterns and the pattern induced delay is non-Gaussian. It is modeled using probability mass functions (PMFs). This article presents an automatic test pattern generation (ATPG) method, where multiple uncorrelated test patterns per path improve its defect coverage (DC). The impact of the ATPG process is evaluated by comparing to traditional methods. It is also shown that the presented ATPG is useful in selecting critical paths.

Functional Constraint Extraction From Register Transfer Level for ATPG

The use of scan test patterns, generated at the gate level with automatic test pattern generation (ATPG) tools in design simulation, was proposed in our previous work to improve verification quality. A drawback of this method is the potential presence of illegal (or unreachable) states (ISEs) causing unwanted behavior and false error detection in the verification process. In this brief, we present a new automated tool that helps overcome this problem. The tool extracts functional constraints at the register transfer level on a VHDL description (it can be easily adapted to any other hardware description language). The constraints extracted are used in the ATPG process to generate pseudofunctional scan test patterns which avoid the ISEs. The whole verification environment incorporating the proposed tool is presented. Experimental results show the tool impact on the reduction of false error detection in verification. In addition, it shows the verification quality improvements with the proposed environment in terms of coverage, time, and complexity.

On Acceleration of SAT-Based ATPG for Industrial Designs

Due to the rapidly growing size of integrated circuits, there is a need for new algorithms for automatic test pattern generation (ATPG). While classical algorithms reach their limit, there have been recent advances in algorithms to solve Boolean Satisfiability (SAT). Because Boolean SAT solvers are working on conjunctive normal forms (CNFs), the problem has to be transformed. During transformation, relevant information about the problem might get lost and, therefore, is not available in the solving process. In this paper, we present a technique that applies structural knowledge about the circuit during the transformation. As a result, the size of the problem instances decreases, as well as the run time of the ATPG process. The technique was implemented, and experimental results are presented. The approach was combined with the ATPG framework of NXP Semiconductors. It is shown that the overall performance of an industrial framework can significantly be improved. Further experiments show the benefits with regard to the efficiency and robustness of the combined approach.

SAT-based ATPG using multilevel compatible don't-cares

In a typical IC design flow, circuits are optimized using multilevel don't cares. The computed don't cares are discarded before Technology Mapping or Automatic Test Pattern Generation (ATPG). In this paper, we present two combinational ATPG algorithms for combinational designs. These algorithms utilize the multilevel don't cares that are computed for the design during technology independent logic optimization. They are based on Boolean Satisfiability (SAT), and utilize the single stuck-at fault model. Both algorithms make use of the Compatible Observability Don't Cares (CODCs) associated with nodes of the circuit, to speed up the ATPG process. For large circuits, both algorithms make use of approximate CODCs (ACODCs), which we can compute efficiently. Our first technique speeds up fault propagation by modifying the active clauses in the transitive fanout (TFO) of the fault site. In our second technique, we define new j - active variables for specific nodes in the transitive fanin (TFI) of the fault site. Using these j-active variables we write additional clauses to speed up fault justification. Experimental results demonstrate that the combination of these techniques (when using CODCs) results in an average reduction of 45% in ATPG runtimes. When ACODCs are used, a speed-up of about 30% is obtained in the ATPG run-times for large designs. We compare our method against a commercial structural ATPG tool as well. Our method is slower for small designs, but for large designs, we obtain a 31% average speedup over the commercial tool.

Low-power multi-core ATPG to target concurrency

A function-based automatic test pattern generation (ATPG) tool for embedded core testing is presented that reduces test cost and considers test power dissipation of system-on-chip (SoC). Cores are tested concurrently with the use of test functions, as opposed to simple patterns, and by I/O pin allocation on the test access mechanism (TAM) during a compact ATPG process. Turnaround time benefits from pre-existing test vectors, or test functions supplied by the provider of each core. The presented method also targets low-power dissipation by considering the switching activity on the SoC inputs. Experimental results show a significant reduction in the test application time due to the achieved level of concurrency.

Circuit optimization by rewiring

Presents a very efficient optimization method suitable for multi-level combinational circuits. The optimization is based on incremental restructuring of a circuit through a sequence of additions and removals of redundant wires. Our algorithm applies the techniques of automatic test pattern generation (ATPG), which can efficiently detect redundancies. During the ATPG process, certain nodes in the circuit must have particular logic assignments for a test to exist. Based on the properties of these mandatory assignments, we have developed theorems to eliminate unnecessary wire redundancy checking. This results in a significant performance improvement. The fast run time and the excellent scaling to large circuits make our Boolean optimization method practical for industrial applications.

Broadcasting test patterns to multiple circuits

Scan designs can alleviate test difficulties of sequential circuits by replacing the memory elements with scannable registers. However, scan operations usually result in long test application time. Most classical methods to solving this problem either perform test compaction to obtain fewer test vectors or use multiple scan chain design to reduce the scan time. For a large system, test vector compaction is a time-consuming process, while multiple scan chains either require extra pin overhead or need the sharing of normal I/O and scan I/O pins. In this paper, we present a novel test methodology that not only substantially reduces the total test pattern number for multiple circuits but also allows a single input data line to support multiple scan chains. Our main idea is to explore the "sharing" property of test patterns among all circuits under test (CUT's). By appropriately connecting the inputs of all CUT's during the automatic test-pattern generation process such that the generated test patterns can be broadcast to all scan chains when the actual testing operation is executed, the above-mentioned problems can be solved effectively. Our method also provides a low-cost and high-performance method to integrate the boundary scan and scan architectures. Experimental results show that 157 test patterns are enough to detect all detectable faults in the ten ISCAS'85 combinational circuits, while 280 are enough for the ten largest ISCAS'89 scan-based sequential circuits.

Testability measure with reconvergent fanout analysis and its applications

Many testability measure tools have been developed to reduce computational complexity of automatic test pattern generation (ATPG). These tools, by using linear algorithm or heuristics, obtain quantitative testability measure for each line within a circuit. Such testability measure is usually based on the measures of controllability and observability which do not always reflect the real situation of testability. One reason for this is that reconvergent fanouts can sometimes cause redundant faults. This paper presents a method of computing testability with reconvergent fanout checking and redundant fault detecting, while keeping a reasonable computation complexity. The result obtained is used to guide design transformations in VLSI high-level synthesis so as to generate circuits which are less costly for both ATPG and testing process.

SOCRATES: a highly efficient automatic test pattern generation system

An automatic test pattern generation system, SOCRATES, is presented. SOCRATES includes several novel concepts and techniques that significantly improve and accelerate the automatic test pattern generation process for combinational and scan-based circuits. Based on the FAN algorithm, improved implication, sensitization, and multiple backtrace procedures are described. The application of these techniques leads to a considerable reduction of the number of backtrackings and an earlier recognition of conflicts and redundancies. Several experiments using a set of combinational benchmark circuits demonstrate the efficiency of SOCRATES and its cost-effectiveness, even in a workstation environment. >